HyperBus (OctoSPI) length matching

[shffhsdfhse]

I'm doing PCB layout and I'm trying to assign pins for the HyperRAM (HyperBus) that will give me the simplest layout.

The app note for the RAM IC has extremely strict length matching requirements. For example, matching between the data lines all have to be within 25 mils of the strobe trace.

My question is with regards to selecting the ports for the data lines. Do I always match trace lengths to the MCU pin? Does it matter whether I use Port1 or Port2, or mix and match Port1 and Port2? For example, Data[3:0] on Port2[3:0], and Data[4:7] on Port1[4:7]? The location of the HyperBus (OctoSPI) pins seem to be all over the MCU.

[Spaced Cowboy]

I don't have an answer for this, but I find myself in the same boat. Did you ever figure it out ?

[shffhsdfhse]

Unfortunately no. There doesn't seem to be good documentation about HyperBUS anywhere. Even the HyperBUS memory vendors have very limited information, and they don't have information when you submit support tickets.

I'm guessing that the best approach is to follow any guidlines you can find and then hope for the best. I even tried simulating using IBIS models from the memory vendors and I don't think I was getting particularly good simulation results.

[Spaced Cowboy]

Well, that *****!

Thanks for getting back to me, and quickly too 🙂

I guess I'll regard the Hyperram part of the project as "experimental" and see how it goes. I did post the question again, but it's not getting any traction as yet...

[shffhsdfhse]

I think the issue is that this memory, and the memory-controller peripheral support for it, is still relatively new and probably not that popular. However, when you need decently fast and large memory in a small package, it's hard to beat.

I can't say for sure, but I suspect a lot of the layout requirements are overly strict. I looked at some of the layouts on the demo kits, and it seems like they have errors but it still work (or they are just doing something I don't understand). I did some rules-of-thumb from my SI textbooks, and the demo kits seem to violate them pretty badly. However, modern driver circuits are more advanced than just a regular rise-time style calculations would suggest, so go figure. But I guess that is the problem with this approach, we don't want to guess or just horribly overdesign everything.

I think the most likely answer you are going to get are to simulate the signal integrity using the actual PCB layout and IBIS models, but those tools are expensive and not widely accessible.