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Strange Values in AGC and internal status display register.

SStad.3
Associate II

Hi everyone,

I designed my own board for the St25ru3993. Now I am trying to ramp up the RF Field. But before I can do that i need to check if the PLL is locked and the oscilator signal is stable. So i read the AGC and internal status display register. In my case the osc_ok bit and the pll_ok bit are not set, but the rf_ok bit is set. How is that possible? rf_ok bit should be set when field ramp up is done.

What could be the reason for the osc_ok bit not being set? And how to lock the pll?

Thanks in advance

1 ACCEPTED SOLUTION

Accepted Solutions
Bart Herse
Senior II

Hello SStad.3,

which firmware is used to start-up the reader?

Is it ST firmware or a self developed version?

In any case - check the following:

  • if the oscillator bit is not set then the PLL cannot lock either
    • is a XTAL or a TCXO used?
    • is the 20 MHz reference present?
  • is the reader IC configured correctly for XTAL or TCXO - check register 0x0E.

if the 20 MHz reference is OK continue with the items below:

  • automatic or manual VCO segment selected?
    • refer to the VCO tuning range selection in the datasheet of ST25RU3993, section 2.3.1
    • with the automatic VCO range selection the reader will select the best VCO segment.
  • which frequency is set?
    • check the PLL main register for value A and B
    • check the correct settings of A and B according to the formula shown in the datasheet under 2.3.2.
  • check the loop filter which is connected to pin LF_CEXT (pin 45)
    • are the components correctly installed and do they have the correct values

When the reader is connected to a spectrum analyzer at which frequency is the reader output detected?

When it is purely a PLL locking issue then the carrier frequency will be instable.

I hope the items above are helping to solve the issue.

Cheers,

B

View solution in original post

8 REPLIES 8
Bart Herse
Senior II

Hello SStad.3,

which firmware is used to start-up the reader?

Is it ST firmware or a self developed version?

In any case - check the following:

  • if the oscillator bit is not set then the PLL cannot lock either
    • is a XTAL or a TCXO used?
    • is the 20 MHz reference present?
  • is the reader IC configured correctly for XTAL or TCXO - check register 0x0E.

if the 20 MHz reference is OK continue with the items below:

  • automatic or manual VCO segment selected?
    • refer to the VCO tuning range selection in the datasheet of ST25RU3993, section 2.3.1
    • with the automatic VCO range selection the reader will select the best VCO segment.
  • which frequency is set?
    • check the PLL main register for value A and B
    • check the correct settings of A and B according to the formula shown in the datasheet under 2.3.2.
  • check the loop filter which is connected to pin LF_CEXT (pin 45)
    • are the components correctly installed and do they have the correct values

When the reader is connected to a spectrum analyzer at which frequency is the reader output detected?

When it is purely a PLL locking issue then the carrier frequency will be instable.

I hope the items above are helping to solve the issue.

Cheers,

B

SStad.3
Associate II

Hi Bart,

I'm writing my own Code by manipulating the registers via SPI

Now I configured the IC for the TXCO. The status register indicates that the reference frequency is stable.

I tried the Automatic VCO segment selection direct command, but the IC never sends the IRQ. But I also tried other commands like soft_init, this one produces an IRQ. You can see the external parts of the loop filter in the picture at the end. The frequency set, is the standard value of the registers (it should be 867MHz by default), because I just want to ramp up the field for now. I will try to measure the output with a spectrum analyzer next week. Is there maybe a known configuration of the pll section that works ?

Thanks for your help

SStad.3
Associate II

0693W00000DlPdiQAF.png

Bart Herse
Senior II

Dear SStad.3,

the loop filter values are correct assuming the final assembly is correct as well.

How many boards are affected by the non locking PLL symptom?

As for the question in you post before asking for known VCO segment settings.

It is possible to set the VCO segment manually as well.

Here is a table that shows for which frequency range which VCO segment should be chosen:

0693W00000DlQBqQAN.jpgThe VCO segment value should be entered into the lower nibble of register 0x11.

Note that the automatic VCO selection should be disabled first by using the direct command 0xA5

The included MVCO Result corresponds to the frequency boundaries.

As it can be seen the target for the segment selection is to keep the MVCO result between 3 and 5 in order to maintain best linearity of the KVCO characteristic.

Information about the MVCO measurement and how it is done refer to the datasheet, section 2.3.1 (VCO control voltage measurement).

Hope this information helps to get the PLL locked.

Cheers,

B

SStad.3
Associate II

Ok, so I tested your recommendations. I think the problem is that the 0xA5 and 0xA4 commands are not producing an interrupt. Other commands like Soft_Init do produce interrupts. So I guess the VCO commands are not working. If I assume that it is working even when there is no interrupt and continue with the MVCO, the MVCO result is just 000.

SStad.3
Associate II

Should I be able to measure some voltage at the external part of the loop filter?

Hi SStad.3,

how are the registers 0x35 and 0x36 configured in your case?

Cheers,

B

Hi SStad.3,

the VCO voltage is measured best between R33 and C55 referring to the HPEV reader.

HPEV also has a test point there.

Cheers,

B