ST25R3918 NFC read power optimzation

[BillR]

Hi,
we're working with the ST25R3918-AQWT in a design that's powered by a CR2054 coin cell. We're trying to minimize the peak current draw through the NFC coil since right now we're seeing about a 500mV droop on VBAT during our NFC read. 

We've already configured the output resistance to the highest setting but we're still seeing peak current spikes that are higher than we’d like. Our main concern is an effective reduction in battery life if the voltage droops enough to brown out the ST25R3918 whenever the field turns on. Are there any other settings or hardware design choices we can make to reduce the total energy used during an NFC read? 

Additional information:

• Our overall field-on time is 10msec. We believe this is about as fast as we can make an NFC transaction
• On our application, the NFC tag is a fixed distance from the ST25R3918. Currently we have about 2-3x more range than we need. 
• We already have about 1200uF of capacitance on VBAT to help with this voltage droop issue
  
  

• Changing the TX modulation to 5% and maximum driver resistance to max. did help already, reducing the drop by 100mV. 

• Attached is a capture of the VBAT droop during an NFC read
  
  

  Current draw during the NFC read. 
  
  
  Thanks for any ideas you have, Bill. 

[Ulysses HERNIOSUS]

Hi Bill,

which d_res setting are you using? A setting for factor 4, right?

You can still try to reduce the VDD_DR setting (reg_s + rege bits). Which settings are you currently using (rege/reg bits)?

Going from 12% to 5% modulation I would more expect an increase in current, less switching more levelled out. But of course you are moving out of the compliant settings range - will likely still work for most tags. Which NFC technology are you using?

In the end you might want to change the matching to something higher-ohmic.

BR, Ulysses

[BillR]

Hi Ulysses,

Thanks for the suggestions. All we are doing is looking for the presence of a tag that should be permanently within a short distance of the reader, to detect its missing or cut, checking the tamper status. 

We're currently using d_res = 14, so just below the high-Z setting. That still gives us consistent tag reads at our fixed, close range, and it helped significantly in reducing peak current — we saw about a 100 mV improvement in VBAT droop during the NFC read after making this change.

We had also set am_mod = 0 (5% modulation), but since we're using ISO14443A — which uses OOK, not AM — we now realize that setting has no effect in this mode. So the improvement we observed is attributable solely to the reduced driver strength via d_res.

We haven’t yet adjusted the VDD_DR setting — we’re still using the default values for reg_s and rege. I’ll look into lowering this next to see if we can squeeze out further power savings during modulation. If you have recommended starting values for the lower end of that range, that would be helpful.

We're also working with our RF consultant to tweak the antenna matching to present a slightly higher impedance, as you suggested.

Best,
Bill

[Ulysses HERNIOSUS]

Hi Bill,

are you using our RFAL? If so it should have set sup3V=1, reg_s=0, triggered adjust regulators which may have resulted in good setting of bitfield reg_*. Also worth checking the resulting value.

If not, then please try a manual setup with sup3V=1, reg_s=1, reg_e=5(2.4V). This rege setting is actually the smallest available.

BR, Ulysses

[BillR · Accepted solution]

Hi Ulysses, we’re not using RFAL, just configuring the chip directly. I was just about to try this:  sup3V = 1, reg_s = 1, and rege = 0b0001 for 2.4 V, and confirm the SPI and NFC behavior under that condition.

Thanks! Bill

[Ulysses HERNIOSUS]

Hi,

please beware that rege=0b0001 is not a valid setting for sup3V=1. Please use rege=0b0101!

Ulysses

[BillR]

Sure,  I noticed that but the idea is turning it down to 2.4, thanks! 

Bill