Triac triggering circuit with a positive power supply

ahmed239955_st · ‎2016-11-30

Posted on December 01, 2016 at 00:27

After reading AN3168 I found a paragraph that I do not actually understand and seemed weird for me .

Page 8, ''With the bipolar solution, to keep the current sourced to the gate, the only way is then to use a PNP transistor.''

Do you have any explanation for this sentence please ?

And what is the consequence of using NPN instead ?

Thanks in advance.

Benoit RENARD · ‎2016-12-01

Posted on December 01, 2016 at 11:04

Hello Ahmed,

This sentence is related to the Figure 7, that shows a Triac controlled with positive current applied to the gate (i.e. a triggering in Q1 and Q4 quadrants, refer to Figure 3 for quadrants definition).

Then, if you want to drive the Triac with a positive current, the gate current path is:

- Sunk from VDD through the PNP transistor,

- Through the resistor to the gate

- flowing in the gate to A1 Triac internal junction

- and finally the Triac A1 is referenced to VSS.

As a bipolar transistor is an unidirectionnal device, a NPN transistor cannot be used to drive the Triac with a positive gate current and this circuit.

A NPN transistor can be used if you drive the Triac with a negative gate current (i.e. a triggering in Q2 and Q3), as shown in figure 8. In this case, A1 is referenced to VDD (Triac A1 and A2 are inversed compare to previous schematic), the current flows from A1 to Gate, and then through the NPN transistor to VSS.

I hope this is more clear, don't hesitate if you have any other queries.

Best Regards

Benoit

ahmed239955_st · ‎2016-12-01

Posted on December 01, 2016 at 13:38

Thanks Benoit for your reply, All you have mentioned is clear.

But I just have a question about what could happen if I used a NPN With this configuration below (

http://imgur.com/a/BNa6l

).

http://imgur.com/a/BNa6l

Where ''Control'' is connected to GPIO of the MCU .

Also what if the GPIO pin of the MCU is connected directly to the gate of the triac (for positive triggering) , could this lead for current to sunk out of the gate terminal ?

The supply voltage of the MCU is from a non-isolated buck converter in both cases .

Thanks for your help.

ahmed239955_st · ‎2016-12-01

Posted on December 01, 2016 at 13:38

Thanks Benoit for your reply, All you have mentioned is clear.

But I just have a question about what could happen if I used a NPN With this configuration below (

http://imgur.com/a/BNa6l

).

http://imgur.com/a/BNa6l

Where ''Control'' is connected to GPIO of the MCU .

Also what if the GPIO pin of the MCU is connected directly to the gate of the triac (for positive triggering) , could this lead for current to sunk out of the gate terminal ?

The supply voltage of the MCU is from a non-isolated buck converter in both cases .

Thanks for your help.

Benoit RENARD · ‎2016-12-01

Posted on December 01, 2016 at 14:14

It will work if the MCU is able to applied a voltage at least equal to the NPN Vbe sat max + the maximum VGT of the Triac (both junction have to be polarized to allow current path).

But the real problematic will be the EMC, for example the immunity to Electrical Fast Transcient. When Triac is not controlled, the transistor Emitter is not referenced, induces a poor robustness against faulse triggering in case of high dV/dt.

An alternate solution using your schematic is to add a resistor between Triac gate and GND (for example 330 Ohm). Immunity of the circuit will be better, but always lower than solution proposed in the Application Note, and it works well with a non-insulated buck converter.

Let me know if you need more details,

Benoit

Benoit RENARD · ‎2016-12-01

Posted on December 01, 2016 at 14:35

Regarding gate directly connected to the MCU I/O port (with an intermediate resistor sure), see section 2.1 of the same application note.

The polarity of the current on the gate depends of your converter reference to A1.

The transistor stage between MCU and Gate is only used in case the MCU I/O pin cannot deliver enough gate current to trigg the Triac.

For the BTA16-600CW, the Triggering current specified IGT is 35 mA. Be sure the max sunk current by MCU I/O pin is higher than 35 mA. You can also use two - or more - I/O pins in parallel to provide enough current. Or also to use a Triac with a lower IGT, for example the BTA16-600SW with a IGT at 10 mA.

Another remark: In your figure, the Part/Number of the Triac is a BTA16-600CW. Please note that this is 3 quadrants Triacs, that work only in quadrant Q1, Q2 and Q3, and then not in Q4. So if you want to trigger the device in both polarities of power network voltage, use a 4 quadrants device (i.e. BTA16-600C). Or use a negative current control (Figure 6 or 8 of the Application Note).

Let me know if all is clear.

ahmed239955_st · ‎2016-12-01

Posted on December 01, 2016 at 16:45

Great informative reply Benoit. Thanks.

Actually two question arises here. The first is: I have tried the NPN solution as figure 1 is works as you said, but when trying it again, the MCU blew up !! do you have a explanation for this ? (as this has been very confusing to me).

The second question is related to this sentence in your last reply ''

The polarity of the current on the gate depends of your converter reference to A1''.

Sorry it is not so clear . please note that the converter ground is connected to the A1 .

Also about the Triac itself, yes I have use BTA-600C (4 Quadrant Triac) but forgot to edit that in ''figure 1''. Thanks for note .

I have heard that ST will close the forum temporarily, so if we can communicate through email, it will be very appreciated.

Thanks for your valuable support.

Benoit RENARD · ‎2016-12-02

Posted on December 02, 2016 at 09:19

mailto:benoit.renard@st.com

Hello Ahmed,

For the MCU blew-up, I don t see any reason, this is a typical schematic uses for a long time.

Regarding the polarities of the gate current,:

- In Figure 5: A1 has the same reference than the power supply (VSS), the gate current flows into the gate from VDD to VSS => Positive gate current (Q1 and Q4 control)

- In Figure 6: A1 is referenced to VDD, the gate current flows through A1 and is sunk out of the gate to VSS => Negative gate current (Q2 and Q3 control).

Hope it helps and dont hesitate if you have any question,

Benoit

ahmed239955_st · ‎2016-12-05

Posted on December 06, 2016 at 07:28

Thanks

for your help and congrats for the new forum .