Hello ,
I'm using the STGAP2SiCD gate driver IC to my application as a power conversion unit.
I have some question about VDD pin and each logic input's voltage level.
In my application, I connceted 3.3V to VDD and used MCU PWM output pin to INA(3.3V),
and BRAKE, SD, iLOCK pin pull high to VDD.
but i can't earn any enerage from gate driver IC to let MOS turn on,
In datasheet, I observe the input logic condition -- Vil and Vih
these pin record the output signal transfer's thershold voltage.
it means if this input logic INA greater than 0.72*3.3V(VDD) than output VHA and GON_A pin will short.
but I can not gate correct waveform from this driver IC.
I think I can fully satisfy this condition.
And if I used 5V to VDD,and used same condition MCU PWM output pin to INA(3.3V),
it will have correct waveform, but I have some question about this driver IC.
in worst case,the INA pin cannot fully satisfy greater than 0.72*5V(VDD).
but it have correct waveform.
Is my undestanding about this thershold rule wrong or Is there anything else I need to know?
Thank you in advance.
