L6982CDR application problem.

[PL3]

Hi,We're encountering an issue with the L6982CDR buck converter in our application. Here's the detailed scenario: Configuation: We're using it to convert a 24V input to a 5V output to power the board. Load: The 5V output supplies a load current of approximately 200mA. System Context: The same 24V input is also used to drive a stepper motor. Problem:Following mass production, some units have experienced a loss of the 5V output. The occurrence rate of this failure is low. Key Observations: This fault occurs during operation, not at power-up. The fault clears if the 24V power is restarted. When the failure happens, we measured a normal 24V input voltage and a normal voltage at the VCC pin of the IC. However, the SW pin output remains low. Notably, we have used this chip reliably for a long time, and this is a recent issue.

Here is the schematic of our product：

Here is the PCB of our product:

Please let me know if anything is unclear or if you need any tests performed We would appreciate your guidance on troubleshooting this.

[Peter BENSCH]

Welcome @PL3, to the community!

You probably connected the stepper motor to VCCMT and thus decoupled it from the L6982 via FL2? What is the inductance of FL2?

Nevertheless, depending on the operating conditions, overvoltage pulses from the motor can have a retroactive effect on the L6982 and possibly cause the problem you observed. This could result in a latch-up effect or maybe the overvoltage protection being triggered.

Your layout looks good, at least in the visible area. Unfortunately, the presumably large GND plane, to which many GND vias are connected, is not shown. Have you considered separating the current paths cleanly, e.g. by using star-shaped GND routing?

Regards
/Peter

[Wtm]

Hello,Peter

My colleague PL3 is on leave, so I am now handling this matter.

In our design,connected the stepper motor to VCCMT and thus decoupled it from the L6982 via FL2（Wurth 742792651）

Our design uses a 6-layer PCB with complete ground plane layers, as shown in the figure below.

The failure recurrence rate is currently quite low in our case, occurring only about once a month. Do you have any suggestions for testing methods or design improvements?Looking forward to your reply！

Regards

[Peter BENSCH]

Do you have any further information about the failure?

For example, is the motor being turned backwards from externally?

[Wtm]

The failure occurs during the product aging test process, involving forward and reverse switching of the motor with intervals in between, but without external reverse rotation. Below are some failure test waveforms:

SW PIN

BOOT PIN

VCC PIN

[Peter BENSCH · Accepted solution]

My only suggestion is to revise the layout. It is important to observe the basic design guidelines for switching regulators:

• clean separation of the main current path and sensitive surroundings (feedback line, etc.) instead of a large, shared GND plane
• route the main current path on one level without vias if possible
• etc

Regards
/Peter

[Wtm]

Hello,Peter

Are there any good power supply examples with star grounding routing recommendations? The recommended layout in the L6982 datasheet doesn't cover this aspect .

Regards

[Peter BENSCH]

After taking a closer look at your layout, I can't see significant problems. The pin FB is very close to the buck coil, but small enough not to pick up switching signals if the buck coil is not magnetically shielded.

However, I think I have found a bigger problem: choke FL2 is only an EMI suppression ferrite bead, whose inductance is probably not sufficient to keep steep pulses from the motor away from the buck converter. Please replace it with a coil with significant larger inductance, e.g. 1...2mH and enough current capability.

Regards
/Peter

[PL3]

Hello Peter：

If it is a latch-up effect, would the failure symptoms match what we are experiencing: normal input voltage, zero output voltage, and output recovery only after completely power cycling the board?
From what I've seen in the datasheet, overvoltage and overcurrent protections typically resume output automatically once the fault condition is removed, without requiring an input power restart.

I notice that the measures you mentioned seem to focus on optimizing trace layout to avoid latch-up effects. Can you specify under what circumstances the L6982 might experience latch-up? I would like to try to reproduce the failure. What deliberate measures can I take to replicate the issue and thereby verify whether it is indeed caused by latch-up?

Regards