Posted on March 21, 2012 at 16:59Hello Iurie,
1. If I use an external 3.3v to drive both Vreg and Vdd (internal reg disabled), do I still need a 40uf Vreg cap or I can use just one 10uf?
In this case you could use a 22uF capacitor (the 10uF required by VDD input + some extra for the logic supply). If an electrolytic cap is used, you need to add a 100nF ceramic capacitor next to VREG and VDD pins.
2. Can I use Vs bulk capacitor with lover value but better ESR? ESR and Ripple current is primary parameters for Vs bulk cap, am I right?
This statement is true for the ceramic capacitors filtering the current pulses required by PWM operation. In the suggested layout you should place a 100nF ceramic cap near VSA pins and a 100nF ceramic cap near VSB pins.
The bulk capacitor is bigger and it can have higher ERS. Its function is to supply the charge to the system during load variations (e.g. when you switch from holding to acceleration current). It should be sized according to the maximum load current variation and the parasitic inductance between the main power source and bulk.
The 100uF mounted on EVAL6470H boards is sized considering worst conditions (you supply the board through long wires requiring strong load variations), but you could reduce this value according to your real application.
3. Is the SW pin still 5v tolerant when external Vreg = Vdd = 3.3v?
Yes, it is. But please note that the SW input is pull-upped to VDD. If you apply 5V to the pin in this condition a current is sourced to your 3.3 supply.
Regards
Enrico
