L5970AD DCDC schematic doubt

[AlexMachine]

Hello,

I am investigating in using L5970AD DCDC converter for a 12VDC to 3V3 need.

It was advised to me by the ST DCDC online simulator.

It's a 20 year old circuit but it it matches the budget, the additional BOM and the efficiency so I am interested.

But I don't reach in answering some questions. If one of you can share some return of experience about this chip I am gladly listening.

I am in design phase, looking datasheets, and except error I don't find my answers :

- The VREF signal is noticed as 3V3. 3V3 is the output I want to create. On the Typical application schematic it seems not clear for me if connecting VREF to the output is okay, or if we need a precursor 3V3 ??? Should we supply a high impedance 3V3 from resistor divided input for example ? I couldn't reach advise about it, the is no paragraph about VREF. Is it an input or an output? What about generating 5V, do we need a 3V3 rail ?

Also, even if switching frequencies are different, why not group L5970AD and L5970D in one unique datasheet ?

Thank you for reading,

A++ Alex

[Richard Li]

In table 5 , Electrical Characteristics, under Sync function, look for "high input voltage" the maximum voltage is Vref.

So if SYNC signal is 4V, it is higher than inside Vref-3.3V.

[AlexMachine]

@Peter BENSCH ok you had the solution mark but we are still wanting to discuss with you ^^^^^

[AlexMachine]

Okay yes I see it.

I believe SYNC is either NC or to an other SYNC so no risk. Maybe some TVS diode for maniac design? ^^^^   Maybe you want to feed SYNC with an other signal?

[AlexMachine]

I understand DCDC regulation with duty cycle but when it is frequency, I just trust chip designers for now

[Richard Li]

In datasheet, if you want different frequency, you can use SYNC feed external signal (table 3) 

[AlexMachine]

Okay interesting. 

I imagine changing nominal frequency can help in reducing component size or displace EMI spectrum?

Please Richard, how would you use this VREF? It is poluted and High Z. 

[Richard Li]

High frequency can use lower value inductor, it can reduce design area, so most DCDC try increase frequency, of cause it is more difficult compare lower frequency.

For example, higher frequency stability is more challenge.

[Richard Li]

I didn't use it, I did attached two examples in early ST document, please look my early attachment.

[AlexMachine]

A VREF of 3.6V would be more interesting so we can drop with better regulation (LDO, Ref chip).

I wonder what to do with this 3v3 and I would have liked more clearance in datasheet with a signal type colum in pinout table, to be constructive.

For a 5mA poluted ref I prefer a zener or a resistor divider.

Open

[Richard Li]

Attached again, page 15