STNS01 data sheet dated 14-Dec-2017, Revision 4, schematic is enclosed.
What precaution are recommented to prevent the chip going into oscillation. On value of Cap, pcb trace length, rated voltage (MLCC capacitance drops when DC is a good percentage of the maximum rated voltafe) and physical size. Does size affect ESR, equivalant serial reactance.
Time ago, first generation 3 terminal regualtor 7805-type has quite strict specification on by pass capacitor, likely due to small phase margin of the chip amplifier and feedback. Wonder if these may be relaxed somewhat nowadays.
Pointer to reading notes specific to STNS01 is appreciated.
If we wire up the chip and it does NOT oscillate. How to determine system phase margin to see if it is safe and far away from oscillation threshold point or it is getting dangerously close to the point of starting oscillation ( when temperature or cell impedence changes)
Best regards
