2009-05-11 09:27 AM
2011-05-17 12:58 AM
Is it possible to use SSP in SPI mode with open collector MOSI output?
I need this for some multimaster & multislave environment... Actually, i'm testing with only 1 master (STR9) and 1 slave (SD Card), CPOL = 0, CPHA = 0, MOSI pulled to 3V3 by 47k resistor. Since writing a '1' to MOSI output pin now pulls the MOSI line to ground, i write the complement of the data into the SSP TX FIFO. The problem is, that if i want to shift out a '1' (i.e. setting the MOSI pin to '0') the data bit is shifted out on rising edge of clk, not on falling as it should be. So the data is shifted out at the same point in time when as it is captured by slave.....of course this doesn't work.... Is this a bug? Is there some workarround? Attached is a trace of the SPI with MOSI in open collector mode and in push/pull mode (that's how it should be). regards, daniel2011-05-17 12:58 AM
I will more suspect a too high value for your pull-up resistor.
47k for a 400kHz bus seems too high, try something like 4k7 instead and check your MOSI signal with an analog scope (in your drawing it seems to change at the rising edge of CLK, but I am quite sure it is just by chance because it is delayed by half the CLK period by the too high pull-up resistor value). Hope it make sens, let us know.2011-05-17 12:58 AM
Hi jomedfree,
thanks for your reply. you were right, the problem is the pull-up resistor.... i replaced 47k by 4k7 resistor and now the MOSI signal looks much better (at least during initialization with 400kbps). After initialization i query max. transmission speed from the SDC/MMC and switch to a maximum of 12Mbps. at that speed, a 4k7 resistor is still too much, so i'll have to check whether i can decrease the pull up even more (although 4k7 isn't really much at all....) or maybe even need a different design with push/pull output...... regards, daniel