Pushing ST7LITE ADC to its limits

[fggnrc]

Posted on June 04, 2007 at 12:32

Pushing ST7LITE ADC to its limits

[fggnrc]

Posted on June 04, 2007 at 06:46

I am developing a 50 Hz AC power meter.

To have the instant power, I need to acquire both the current and the line voltage. The 3.5 us conversion time of ST7LITE ADC matches well with this requirement. The ADC data register layout slowers however the processing the 10 bit readouts. To minimize the delay between the acquisitions, I have to push the ADC to its limits. In my prototype, a signal proportional to the AC current is connected to pin PA4 of a ST7FLITEUS5, while a signal proportional to the AC voltage is linked to PA2 where I plan to use the input capture function to measure the frequency. The acquisition is triggered every 100 us by the output compare feature of the 12 bit auto-reload timer. These specifications lead to the following interrupt service routine: ADC_ISR ; Clear the interrupt source LD A,PWM0CSR ; Setup the ADC LD A,#$24 ; ADC = on; Channel = PA4 LD ADCCSR,A ; This starts the current acquisition MUL X,A MUL X,A LD X,#$22 ; ADC = on; Channel = PA2 INC A ; Any 3 clock cycles instruction is ok LD A,ADCDRH ; Reads the higher 8 bits and starts a new acquisition LD ADCCSR,X ; Aborts the acquisition from PA4 and restarts it from PA2 LD X,#0 SLL A RLC X SLL A RLC X OR A,ADCDRL LD I_L,A LD I_H,X LD X,#0 ; Now the PA2 acquisition is done LD A,ADCDRH LD ADCCSR,X ; Stops the ADC RIM ; This lets the other ISR run SLL A RLC X SLL A RLC X OR A,ADCDRL LD V_L,A LD V_H,X ; Schedule the next 100 us call LD A,DCR0L ADD A,#$20 LD DCR0L,A LD A,DCR0H ADC A,#$03 AND A,#$0F LD DCR0H,A IRET According to the datasheet, the ADC charges a capacitor for 4 ADC cycles, i.e. for 8 clock cycles, since the ADC runs at 4 MHz. Then by 10 successive approximations the new value is read. If I understand well the datasheet, this should leave another 16 clock cycles before the ADCDRL is updated. If it is true, here is what should happen (notice: the time base starts when ADC is activated): 1st case: fADC and fCPU are in phase when t=0 Time 0 - LD ADCCSR,A execution ends and ADC starts charging the capacitor 8 - The ADC capacitor is charged, ADC starts the PA4 quantization phase 11 - MUL X,A execution ends 22 - MUL X,A execution ends 24 - LD X,#$22 execution ends 27 - INC A execution ends 28 - LD opcode (=$B6) is fetched and EOC is set 29 - ADCDRH address (=$35) is fetched 30 - ADCDRH is read, EOC is cleared and PA4 is being sampled again 34 - LD ADCCSR,X execution ends. The PA4 acquisition is aborted, and PA2 acquisition starts 36 - LD X,#0 execution ends 39 - SLL A execution ends 42 - RLC X execution ends. The ADC capacitor is charged, ADC starts PA2 quantization phase 45 - SLL A execution ends 48 - RLC X execution ends 51 - OR A,ADCDRL execution ends. The ADC is doing the 5th approximation 55 - LD I_L,A execution ends 59 - LD I_H,X execution ends 61 - LD X,#0 execution ends 62 - LD opcode (=$B6) is fetched and EOC is set 63 - ADCDRH address (=$35) is fetched 64 - ADCDRH is read, EOC is cleared and PA2 is being sampled again 68 - LD ADCCSR,X execution ends. The ADC is stopped 2nd case: fADC and fCPU are in phase opposition when t=0 Time 0 - LD ADCCSR,A execution ends 1 - ADC starts charging the capacitor 9 - The ADC capacitor is charged, ADC starts the PA4 quantization phase 11 - MUL X,A execution ends 22 - MUL X,A execution ends 24 - LD X,#$22 execution ends 27 - INC A execution ends 28 - LD opcode (=$B6) is fetched 29 - ADCDRH address (=$35) is fetched and EOC is set 30 - ADCDRH is read and EOC is cleared 31 - The ADC starts sampling PA4 34 - LD ADCCSR,X execution ends. 35 - The PA4 acquisition is aborted, PA2 acquisition starts 36 - LD X,#0 execution ends 39 - SLL A execution ends 42 - RLC X execution ends. 43 - The ADC capacitor is charged, ADC starts PA2 quantization phase 45 - SLL A execution ends 48 - RLC X execution ends 51 - OR A,ADCDRL execution ends. The ADC ends the 4th approximation 55 - LD I_L,A execution ends 59 - LD I_H,X execution ends 61 - LD X,#0 execution ends 62 - LD opcode (=$B6) is fetched 63 - ADCDRH address (=$35) is fetched and EOC is set 64 - ADCDRH is read and EOC is cleared 68 - LD ADCCSR,X execution ends. The ADC is stopped The time between the two readouts is 4.25 us (34 clock cycles) if: - the ADCDRL remains unchanged until 24 clock cycles from the acquisition start - when a conversion is aborted or stopped within 8 clock cycles, ADCDRH and ADCDRL content is not lost Are my assumptions true? Any comment will be appreciated! EtaPhi

[laurent239955_stm1]

Posted on June 04, 2007 at 11:55

Hi,

It is recommended to check the EOC bit before reading the data registers (ADCDRH and ADCDRL). The conversion time is always 14 cycles of Tadc, but the data registers are only updated once the conversion is completed. This means that if a conversion is stopped or aborted, the result of this conversion is never available, only the result of the last completed conversion is available. I hope this will reply to your questions. Best regards Laurent

[fggnrc]

Posted on June 04, 2007 at 12:32

Thank you, Laurent for the reply.

My assumptions were worse than the reality... I am happy with my interrupt service routine and a 4.25 us sampling time between two ADC channels is quite a good result! Regards EtaPhi