I have following three concerns related to SPI interface timing of L9825 low side driver IC. Please refer the image below.
1. Do we really need to toggle the clock signal within 100ns after NCS changed from High to low. If this 100ns is exceeded what would be response of driver IC in the SPI command recognition?
2. Why thcld is specified as Max 20ns instead of Min 20ns? Because it is always depends on the operating SCK period.
3.thclch is specified as Min 150ns. So, do we really need to bring SCK to logic high after NCS changed to logic high? If not what would be the behaviour of low side driver SPI interface recognition?
