interrupts

planeetmaa · ‎2006-05-08

Posted on May 08, 2006 at 15:57

interrupts

planeetmaa · ‎2006-04-26

Posted on April 26, 2006 at 11:39

Hi all,

few thinkgs about the interrupts, I dont clearly understand.

Please correct me, if im wrong. I understood that STR7 copies the contnent of IVR register to the location 0x18 in case of IRQ occurs. I.e. if I map internal ram memory to that location, everything should be ok (as its possible for the EIC to alter that memory location). Only thing I have to do to exit interrupt, is to read ivr and clear pending (and peripheral status) bits.

In the application note (interrupt handling for STR7, AN1776) there is noted that three different methods for interrupt entry are available.

First one is something I really dont understand. Named address method. According to that method, I copy base address to IVR higher side and lower half is updated according to the interrupt channel settings. So if I undrestand it correctly, in case of interrupt that address (say 0x40000100) is copied to the location 0x18. So fetch is performed from that address and whats then? Isn't it going to cause core to enter abort, as it cant decode the instruction? There several unused instructions which does not cause the abort, but still, I dont unerstand, how the ISR is found then (core is trying to execute command 0x40000100 ?).

There are few things about implementing third one too. I tried it as following:

copied 0x40000000 to IVR (for higher half)

As linker is linking to the base address 0x4000000, I copied the lower half of the ISR address to the SIR (small code, it wont be beyong 0x4000FFFF).

To the location 0x18 I put the instruction: ldr pc,[pc,#-0x808]

And assuming that EIC is trying to alter the location 0x18, there is flash in that location, so should not be problem. But the only thing is, that it does not work like this... Can you please explain me, what Im missing?

Another question is that is it going to cause additional wait cycle in case I have flash at location 0x0 and EIC is trying to write to location 0x18? At the moment the fastest interrupt entry (ignore EIC, direct b 0x... to location 0x18) is a bit under 40 cycles (best case could be 5 for core and 2 for EIC as I understood, which I can not achieve, even seldom, actually its constantly a bit under 40).

Thanks for your help!

Madis

planeetmaa · ‎2006-04-26

Posted on April 26, 2006 at 13:34

Hi,

Ok. But what about if I write ISR address (base to IVR and lower part to SIR) to IVR register (let it be 0x40000100 higher and lower part together) and put

ldr pc,[pc,#-0x808]

to 0x18. Then it should work, right? As it loads the address recorded in 0xFFFFF818 to pc? And after this I dont have to read ivr anymore, as loading pc from there should take care of it?

BR, Madis

fbordeleau · ‎2006-05-05

Posted on May 05, 2006 at 14:00

Processor : STR712FR2

Q1. I looked in the documentation and I donâ€™t understand what software interrupt are and how they work. Could you desribe it to me please ?

Q2. Could you give me a few examples of what will cause an undefined interrupt ?

Q3. Does an interrupt can be configure to detect an overflow?

Q4. Which document (and/or link) could you refer me ?

Thanks, Frank

planeetmaa · ‎2006-05-07

Posted on May 08, 2006 at 05:31

Hi,

You should check documetation available on ARM homepage. Something like:

http://www.arm.com/pdfs/DDI0210B_7TDMI_R4.pdf

BR, Madis

fbordeleau · ‎2006-05-08

Posted on May 08, 2006 at 15:57

Thanks guys,

it was exacly what I was looking for.

Is it correct to conclude that an overflow or a division by 0 won't generate an interrupt or an exception ?

Frank