EMI Mux bus interface

[johanan]

Posted on October 05, 2007 at 14:44

EMI Mux bus interface

[johanan]

Posted on May 17, 2011 at 09:47

Can any one explain this from the reference manual:

------------------------------------------------------- Mux Mode 1. 8- or 16-bit When configured as a 16-bit data bus, the address output on the EMI bus is shifted by 1 so as to address 16-bit memory devices. For example, writing a half word to location 0x0042 will generate an EMI address of 0x0021 2. Control Signals: EMI_Rdn, EMI_WRHn, EMI_WRLn, EMI_ALE 3. Port Config: a) Port 8 EMI_AD[7:0] b) Port 9 EMI_AD[15:8] c) Port 7 EMI_A[23:16] Chip Select Options Port 5 pin (P5.4-P5.7) - CS0-CS3 Port 7 pin (P7.4-P7.7) - CS0-CS3 -------------------------------------------------- Why there are 2 wr signals and only one rd signal? How do I connect a 16bit wide device(why the address is shifted by 1), or an 8 bit SRAM on 8 bit mux bus. I could not find a timing diagram or a detailed explanation in the ref. manual or data sheet. Thanks

[sjo]

Posted on May 17, 2011 at 09:47

In 16bit multiplexed mode all reads are performed as 16bit, the core will return the high/low bytes as you requested.

Basically A0 is not outputted for 16bit multiplexed operation, in my case A0 of the str9 was connected to A1 of my target device (A0 target pulled low). There are a few examples of connections in the ref manual. Regards sjo

[johanan]

Posted on May 17, 2011 at 09:47

Thanks, but it is still not clear to me.

how do I connect 2 chips of 8x4Mb memory (for example) that have only CS, RD WR? Johanan