Bspi alignement of data

[jorge2399]

Posted on March 27, 2007 at 06:08

Bspi alignement of data

[jorge2399]

Posted on March 22, 2007 at 06:34

Hi all,

I've got a little problem on my bspi link : -> First my str712 is slave on spi link. I transfer data continuously on spi using Tx fifo (filling fifo in timer It). --------------------------------------- My problem --------------------------------------- -> I have a shift of data on the link.so, after all my data (i fill the tx fifo in an It) are shifted ! --------------------------------------- Analysis --------------------------------------- -> In fact, i can begin a spi link when master SS disable, and so fifo is fulled and it works pretty well. -> But , i can a spi link when master SS enable and SCLK too, and so fifo is fulled and my bspi will begin to transmit a part of dat (but not all because the rest will be sent on the next SS and will shift everything) --------------------------------------- solution ???? --------------------------------------- So, i saw in ref manual that i should disable bspi (p235). But i don't see well how to do it exactly in my software in order to align well data. I hope I explained my problem clearly. Thanks for your suggestions Jorge

[kleshov]

Posted on March 22, 2007 at 06:47

Quote:

-> I have a shift of data on the link.so, after all my data (i fill the tx fifo in an It) are shifted ! Shifted? What do you mean? Please explain. Some code would be nice too.

[jorge2399]

Posted on March 22, 2007 at 07:20

hi volius,

So, in the It of a timer (each 16KHz), i fill the Tx fifo as :

Code:

BSPI1->TXR = (u16 ) Tx_Spi[inc++];

But when i begin my spi link, seems to be when i enable bspi periph, I will activate and enter in my Timer It. For the moment, all is normal. STR is slave on link. So, when i fill the fifo (the first time) (in my timer it), i don't know if the master device is enabling or not the /SS pin at a moment . Two possibility : - STR fill its fifo when the SS is disable at the same time. STR will put data on Miso on the next /SS (and it works very well). - STR fill its fifo when the SS is enable at the same time. STR detect a SCLK and a /SS enabled, so STR will going to begin to transfer a part of the 16bits of my fifo. And it will end the transfer of this ''u16'' on the next /SS . But it will continue etc and etc !! [ This message was edited by: jorge50 on 22-03-2007 11:51 ] ________________ Attachments : Tx_Ko.JPG : https://st--c.eu10.content.force.com/sfc/dist/version/download/?oid=00Db0000000YtG6&ids=0680X000006HtC8&d=%2Fa%2F0X0000000aKB%2Fvf4qWIIh7II5e_QWlFU1RjZC_4yZA5hBXypfAhq6.5I&asPdf=falseTx_ok.JPG : https://st--c.eu10.content.force.com/sfc/dist/version/download/?oid=00Db0000000YtG6&ids=0680X000006HtAN&d=%2Fa%2F0X0000000aJq%2FOJXfkJiWMPivOY1.iCBRaR4laBmAo3NYqI_uWlnHP70&asPdf=false

[kleshov]

Posted on March 22, 2007 at 10:47

As far as I understood, you begin filling the trasmit FIFO too late or too early. I would suggest monitoring the status of the SS pin and only begin filling the transmit FIFO when it's safe to do so. Please correct me if I'm wrong.

Regards, - mike

[jorge2399]

Posted on March 22, 2007 at 11:02

I think too that the best way should be to monitore the status of /SS pin.

I'm gonna to try this way. but, maybe, another solution should be using the ''Transmit fifo empty flag'' Interrupt TIE:01. to see .... So thanks for reply volius, i'll reply when i find a smart solutions ! if any others encountered the problem, please let me know how did you resolved it. Regards, Jorge

[jorge2399]

Posted on March 27, 2007 at 06:08

Hi all,

I used the ''Transmit fifo empty flag'' interrupt in order to solve it . That's better, not perfect ! :( I would like to ask to St moderator if the problem of disalignement of spi data is well known and can it be repaired ? In reference manual, the problem is named, but that's far to be clear !!! that's not well explicated. So, please respond and give a sustainable solution !! Because of this problem, i'm wondering if i change my choice and design project concerning ST arm family. Thanks, Regards, Jorge