As I recall ST also spun out that business.
As you mention there was a move to different topologies, and the NAND ECC requirements changed based on error grouping/distributions, along with the devices themselves doing syndrome generation for the Reed-Solomon ECC methods used. Correction was still a host side task, but not one typically done by the ECC generation/checking HW of the STM32 F2 and F4.
Also the device footprints and availability was a huge mess. For data storage applications everyone migrated to eMMC, which hid the underlying NAND arrays, all the ECC, wear-leveling, and block rotation stuff, so the host could have a generic block storage interface akin to MicroSD cards.
