Posted on April 19, 2005 at 11:08i got my HW using STPC VEGA at stable state. and VEGA and C2 has same bus topology and i can assume the things inside the chips are same (.. hmm why should they be different?)
1. poweron reset condition should be obeyd. if this is not, the clocks dont show strapped default action. espescially PCI clk runs at a few hundred KHz not in tens of Mhz.
2. ISA activity dies (does not persisits) after a few seconds action. in this case, PCI conrol sognal also dies. those things such as Power place layout, and return path optimization etc. are designed right,
one thing to consider is all the return clocks. i put the clock buffer in PCI and Memory clock path. and put 22ohms of serial termination one at each clk pin. i raised this value upto a few hundreds ohm. this value is totally rule of thum. signal reflection and glitch is somewhat hard to detect. and control, board trace impedance is usually not easy to set up. check visible clks all the time when every things are set right, the board suddenly fonctioning stably.
(check solderint too. resolder, and wash the flux. and watch the signals.. you shouldnt simply ignore board assembly state..)
wish you a good luck.
oh. read the troubleshooting section at the end of the datasheet.. and follow the steps..
[ This message was edited by: Twitwity on 19-04-2005 14:41 ]
