2002-11-20 04:33 AM
ST9 : DIV2 mandatory when using PLL ?
2011-05-17 02:32 AM
Based on the datasheet, it looks like the DIV2 (see MODER register) is required when using a crystal :
''Since the input clock to the Clock Multiplier circuit requires a 50% duty cycle for correct PLL operation, the divide by two circuit should be enabled when a crystal oscillator is used'' However, how can we reach the ST9 maximum clock speed (24MHz) with a standard crystal ? The easiest solution would have been to clock the micro with a 4Mhz crystal and remove the DIV2 option. Does anyone have tried to remove the DIV2 bit ? Did it work with your design ? Jojo2011-05-17 02:32 AM
I don't actually see a problem doing this, the DIV2 bit is not used in the 92163 USB devices to obtain the correct internal frequency.
Regards Spencer Oliver Anglia2011-05-17 02:32 AM
If you do not use the initial divider-by-2 you may increase your PLL jitter ?