Posted on January 11, 2003 at 06:07 Hi Terry,
1/ Fint is the ST6 internal clock frequency. It corresponds to the main oscillator frequency filtered by the Oscillator Safe Guard (OSG) function. Two operating modes are available:
1. OSG feature disabled: in this mode Fint = Fosc. If a 8MHz quartz is used, Fint = Fosc = 8MHz.
2. OSG feature enabled: In this mode, the ST6 internal frequency is no more equal to the oscillator frequency. The internal frequency depends on the oscillator frequency versus the OSG frequency. The typical OSG frequency is 4MHz at VDD = 5V. If the oscillator frequency is greater than Fosg, the internal frequency will be equal to Fosg (Fint = Fosg = 4MHz). Now, if the oscillator frequency is lower than Fosg, the internal frequency will be equal to Fosc (Fint = Fosc). Finally, if the main oscillator fails, the MCU will be clocked by the Low frequency Auxiliary Oscillator (Fint = Flfao).
2/ The PSCR value affects the timer interval. However, I recommend you to not modify the reset/reload value as there is no real interest to change it. As you mentioned, the PSCR register is composed of 7 bits (PSCR7 bit is not used) which gives up to 7 different clock ratios (/2 up to /12
. An additional ratio of 1 is also available. The clock ratio is then selected by programming the bit PS[2:0] of the TSCR register. To get more information on the subject I recommend you to have a look to the 8-bit timer functional description available in any ST6 datasheet.
Good Luck,
Thierry
[ This message was edited by: Thierry on 11-01-2003 10:38 ]
