Posted on October 26, 2004 at 14:13Hello,
The 1 wait-state for the XFlash must be configured by writing to the XFICR register at address 0x0E'E000. The reset value in 0x000F which is configuring the XFlash access with 15 wait states.
To have 1 wait-stae the value 1 must be written into.
If the register is not defined in your toolchain you can define it as follow:
#define XFICR *(_huge unsigned int *)(0x000EE000)
for Tasking toolchain
#define XFICR *( unsigned int huge *)(0x000EE000)
for Keil toolchain
Concerning the execution speed, if we do not take into account the wait state, then the execution speed is already not equivalent between IFlash and XFlash.
The IFlash is connected through a 32bit data bus while the XFlash is connected through a 16bit data bus.
Some of the ST10 instructions are coded on 32bit (as JMPS, CALLS...).
For these instructions, each fetch on the IFlash which provide the entire opcode.
But when executing from XFlash 2 accesses will be necessary to provide the full 32bit instruction to the CPU.
It is difficult to give a ratio of speed exceution between IFlash and XFlash as it will depend a lot of the code (number of 32bit vs 16bit instructions).
At 48MHz it will give:
- 41,6ns of instruction cycle from IFlash
- 62.5 ns from XFlash, 1 wait state, 16bit instruction
- 135 ns from XFlash, 1 wait state, 32bit instruction
Hope this is clear.
Kenshin
