ST10F276 X-peripherals, X-interrupts design constraints

[tom7]

Posted on June 16, 2004 at 05:02

ST10F276 X-peripherals, X-interrupts design constraints

[tom7]

Posted on June 14, 2004 at 11:57

Does someone knows about hints and pitfalls concerning the new x-peripherals on ST10F276 device ?

How to handle multiple x-interrupt sources hooked to one x-vector without loosing external events... I have to handle CAN1/CAN2 Rx-Int., XASC-Rx and Tx, XSSC-Rx and Tx Interrupts but there are just these 4 x-vectors... ??? Any idea/proposal ? thx, tom.

[najoua]

Posted on June 15, 2004 at 12:31

When different sources submit an interrupt request, the enable bits (Byte High of XIRxSEL register) define a mask which controls which sources will be associated with the unique available vector. If more than one source is enabled to issue the request, the service routine

will have to take care to identify the real event to be serviced. This can easily be done by checking the flag bits (Byte Low of XIRxSEL register). Note that the flag bit can provide information about events which are not currently serviced by the interrupt controller (since masked through the enable bits), allowing an effective software management also in absence of the possibility to serve the related interrupt request: a period polling of the flag bits may be implemented inside the user application. There is one priority for all Xperipherals sharing the same XPzIC register. For example, If you want to configure ST10 in order to have ASC1 Receive and SSC1 Receive using the same interrupt vector XP0INT, when one of these interrupts occurs , the XP0IR flag will be automatically cleared in XP0IC register. You must verify the Interrupt cause by checking the XIR0SEL flags. This can be done by : 1/ Reading Flag x in XIR0SEL regsister; if it is 0 you have no thing to do , if it is 1 you have to clear it by using XIR0CLR register then execute your code. 2/ Reading Flag (x+1) and proceed like 1/ etc... Proceeding like this, you are sure that the flags corresponding to the serviced interrupts are cleared. I hope this will help you[ This message was edited by: Najoua on 15-06-2004 16:03 ]

[tom7]

Posted on June 16, 2004 at 05:02* Does the execution order matter (first clear Interrupt-Request bit, then the code to serve this event) ? * Having 3 isr-sources bound to one x-vector the isr looks like this : event = XIRnSEL; switch(event) { case SOURCE1 : Serve1(); break; case SOURCE2 : Serve2(); break; case SOURCE3 : Serve3(); /* during execution one of the above occurs.... */ break; } Now, following situation : Source3 was the reason for the interrupt. During serving this (while still inside the isr) SOURCE1 or/and 2 occurs. I'm returning from isr, continuing normal prog. execution. My question is, will I lose these event(s) or gets the isr called again ? Any experience/knowledge about that out here ???? cy, tom.