ST10F276 Read setup time

[urik]

Posted on March 07, 2006 at 08:45

ST10F276 Read setup time

[urik]

Posted on March 07, 2006 at 03:15

Hello,

what is the data set-up time when i use the demuxed bus, with no read delay? is that T15 ? if so does it means that the setup time is 18.5 ns? or if i use a 55 ns SRAM i can latch the data after 55ns and not 55 + 18.5 ns? thanks, Uri.

[najoua]

Posted on March 07, 2006 at 05:12

Hello,

Yes, the data set-up time when using the demuxed bus, with no read delay is t15. If Fcpu = 40Mhz: t15= 18.5 + tc (ns) & tc = 2TCL x (15 - MCTC) ; with 15 - MCTC is the number of wait states. --> so t15 value is Fcpu and external memory access time dependent. Let's take an example: ST10 Frequency is 40 Mhz. Thus the CPU cycle is 25ns. Assuming that the memory has an access time of 55ns= 25ns + 30ns, in order to access this memory, 2 wait states should be inserted in the EBC cycle. In this case: t15= 18.5 + 25x2 = 68.5ns. If CPU Clock is Variable (from 1 to 64MHz): t15 = 3TCL – 19 + tC. I hope i was clear. Regards, Najoua. [ This message was edited by: Najoua on 07-03-2006 09:44 ]

[urik]

Posted on March 07, 2006 at 05:51

Najoua Hi,

you were not so clear , does the T15 <= 18.5 + Ext mem acc time or T15 <= Ext mem acc time - 18.5 ? if i am not worng for 55ns i need 3 wait states? can you please clear this point? thanks, Uri.

[najoua]

Posted on March 07, 2006 at 07:04

Hi Ukatry,

I will clarify, t15 <= 18.5 + tc; tc = 2TCL x (15 - MCTC) which depends on Fcpu and the number of wait states in order to be able to acceed the memory. For a memory having an access time of 55ns: - at least 2 wait states must be added when Fcpu = 40Mhz because: 55 ns = 25 ns + 30 ns and 30/25 = 1.2 so 2 waitstates are needed. - at least 3 wait states must be added when Fcpu = 64 Mhz because: 55 ns = 15.6 ns + 39.4 ns and 39.4/15.6 = 2.5 so 3 waitstates are needed. I hope it is clear now. Regards, Najoua. [ This message was edited by: Najoua on 07-03-2006 11:39 ]

[urik]

Posted on March 07, 2006 at 08:45

now it is clear , thank you very much.