ST10F269 ADC problems

[stephen239955_stm1_stmicro]

Posted on July 19, 2006 at 18:02

ST10F269 ADC problems

[stephen239955_stm1_stmicro]

Posted on December 13, 2005 at 11:08

I have an intermittent fault with an ST10F269.

Once or twice a day from power up, the ADC does not return correct values. The values read ‘appear’ to be frozen and unrelated to voltages on the inputs. Also, on several occasions, after 2-5 minutes, the ADC will then start working correctly. Has anyone seen the following kind of behaviour of the ADC? A little back ground info. The F269 is configured to have 16 analog inputs, although only 12 are driven (P5.0-P5.11). The remaining 4 are left unconnected. Vref at 4.096V is supplied by a MAX6041AEUR.

[najoua]

Posted on December 13, 2005 at 12:03

Hello,

Had you configured the P5DIDIS register? because for port 5 pins that shall be used as analog inputs, it is recommended to disable the digital input stage via P5DIDIS register. Could you please give me your ADC configuration routine? You will find in attachment an application note dealing with Analog-Digital Conversion Errors and how minimizing them. Best regards, Najoua. ________________ Attachments : 8696.pdf : https://st--c.eu10.content.force.com/sfc/dist/version/download/?oid=00Db0000000YtG6&ids=0680X000006I0M9&d=%2Fa%2F0X0000000bXo%2F37F93HmEox0zlOTvd73TrJWppnijRMYOk31VhoTxH1M&asPdf=false

[stephen239955_stm1_stmicro]

Posted on December 14, 2005 at 07:31

Thanks for the reply Najoua.

I have checked that the P5DIDIS reg is set correctly. I should add, this failure is intermittent, AND it only occurs on 3 boards out of 100. As I have many boards operating correctly, I feel that the software is ‘most likely’ correct. My concern is that I have a marginal hardware issue. I read that ‘overdriving’ the inputs can cause inaccuracy of ADC readings, but could it also cause the ADC to lock-up for a few minutes? The design doesn’t over drive in normal operation. But I can’t be certain that it doesn’t during the power-up sequence. (Due to equipment constraints at the moment, I’m finding it difficult capture power up sequence to eliminate this). Or any other issue that may affect the ADC?

[stephen239955_stm1_stmicro]

Posted on December 22, 2005 at 11:29

Hi Neila. Thanks.

I have taken scope traces of the power-up sequence of my circuit. VAREF is generated by a MAX6041AEUR device, powered by the same ‘VDD’ of the F269. At ‘power on’ VAREF lags VDD for about 100us but then attains and maintains the same voltage as VDD until VDD exceeds 4.098 volts (Setting of the MAX device). The circuit that drives the analog I/Ps is powered while VDD is only at 2.4V and it is another 2ms before VDD reaches 5V. However, although the driving circuit is powered, ‘normal’ circuit operation should mean that the analog inputs are not driven. I'm still monitoring to see if it ever happens. One question I have regarding the use of the MAX6041AEUR device. The MAX device states a maximum VREF output current as 500uA, and the F269 quotes IAREF maximum as 500uA. Is this likely to cause any problems? Another area that concerns me. Some CMOS logic I/O (separate 5V supply, common 0V/VSS) connected to the F269 is fully powered while the F269 VDD is only at 2.4V. (Takes a further 3ms before F269 attains 5v). If one or more of these devices were to apply a ‘logic 1’, is this operating the F269 outside of its ‘Absolute Maximum Ratings’? Could it cause latch up? Happy Xmas. p.s. Not my design, I'm just fault finding it.

[najoua]

Posted on December 23, 2005 at 10:04

Hello,

I had understood that the VAREF pin is powered before VDD. VAREF applied to the ST10F269 before the VDD is out of specifications. Your application must be such that Varef is applied after or at the same time as VDD. This is also valid for power off: VAREF must be removed before or with VDD. Best regards, Najoua. [ This message was edited by: Najoua on 23-12-2005 14:49 ]

[stephen239955_stm1_stmicro]

Posted on January 03, 2006 at 06:47

To hopefully clarify…

The device generating VAREF is powered by the same VDD supply as the F269. I believe that VAREF should never ‘exceed’ VDD, as the MAXIM device is not designed to generate an output voltage greater than its supply voltage. However, until VDD reaches 4.096V (the MAXIM output reference voltage), VAREF is only 10 - 100mV less than VDD. Many Thanks.

[stephen239955_stm1_stmicro]

Posted on January 23, 2006 at 07:09

We now believe that what was percieved as an 'ADC fault' is caused by a component failure on another part of our circuit. And not a fault on the ST10F269.

Thanks for your input. The points raised were a useful design check.

[maho]

Posted on June 14, 2006 at 13:36

Hi!

We also use the ST10F269 with all 16 ADC-Inputs and had the same problem, that all analog values ‘appear’ to be frozen and unrelated to voltages on the inputs, yesterday (the first time). You wrote, that you think of a component failure on another part of your circuit -> whats your last findings to that issue? what was the problem in the end? can you please give me a short feedback! Best regards, Markus.

[jf23]

Posted on July 19, 2006 at 18:02

Do you use a PEC to read conversions to a memory buffer, and generate interrupt at 0 count down to reload the PEC channel?

If Yes, I may have the solution of your problem.