Simmultaneous Interrupt Request

[clanuchnik]

Posted on April 14, 2005 at 05:44

Simmultaneous Interrupt Request

[clanuchnik]

Posted on August 17, 2004 at 12:15

I'm using the ST7LITE05, with internal 1 MHz oscillator and X8 PLL.

The AT Timer interrupts the main program at a 25 KHZ frquency. It makes it twice Output Compare (OC) and Overflow (OF) The LITE Timer is set to interrupt at 1 ms. Because the AT Timer has higher priority then the LITE Timer it seem some LITE timer interrupts are not handled. How can I handle all the interrupts of both timer? Thanks ............ Claudio

[anshul]

Posted on August 20, 2004 at 05:05

ART Timer Interrupt has priority over Lite Timer Interrupt and if they both occur simultaneously then first ART Timer Interrupts (Output compare and Overflow) will be service and then only Lite Timer Interrupt will be service. None of your Interrupts will be missed, once a flag is set an Interrupt will occur until the flag is cleared. But incase you are missing the Lite Timer Interrupt that means you are clearing the flag associated outside your ISR and hence you are missing the Interrupt. Please check your code that you are not clearing some flag unintentionally.

[y2399]

Posted on April 13, 2005 at 11:54

Hi all,

I think that I have a similar problem in my application with ST7FLITE05M. My program only use the Lite Timer Timebase interrupt and some interrupts seems to be missed and not appear. I check my code and no flag are cleared unintentionally. The only operation I make on the LTCSR register is to regulary set the WDGD bit in order to prevent watchdog reset and read the LTCSR register in interrupt subroutine in order to clear the TBF flag. So, some interrupt seems to not appear but I don't know why....

[fggnrc]

Posted on April 13, 2005 at 12:12

Akotronic, how do you set the WDGD bit?

Please, be informed that you can not use a BSET instruction because it reads first LTCSR, sets the bit and writes the result back to LTCSR. This behaviour may clear the TBF flag... Regards, EtaPhi

[y2399]

Posted on April 13, 2005 at 12:16

Thank you very much for your answer. In fact, I set the WDGD bit with:

bset LTCSR,#WDGD So, what kind of instruction can I use to set this bit without reading the LTCSR register ? Thanks in advance.

[fggnrc]

Posted on April 13, 2005 at 12:38

If your timebase is 1 ms, here are the instructions:

LD A,#%00010011 LD LTCSR,A If you selected the 2ms timebase, you have to change the constant to: %00110011 In a few words, you have to initialize the LTCSR with the right value. EtaPhi

[y2399]

Posted on April 13, 2005 at 14:09

EtaPhi,

Thank you very much for your help. The solution I found is to set the WDGD bit during the interrupt subroutine because the period between 2 interrupt is smaller than watchdog timeout period. So with the same instruction (bset) I can reload the watchdog and clear the interrupt flag. All is OK now and running well. Thank you very much for your help. Yann

[fggnrc]

Posted on April 14, 2005 at 04:59

Akotronic,

your solution works, but I would not use it since the watchdog function will be voided. Now your application every ms refreshes the watchdog. Your interrupt routine is perfect and it will be ''fired'' periodically. If somewhere else there is a problem (e.g. an infinite loop), this situation will not be detected... Regards, EtaPhi

[y2399]

Posted on April 14, 2005 at 05:44

EtaPhi,

You're right. This method has no interest to use the watchdog because infinite loop will not cause a reset. In the ST7LITE0/ST7SUPERLITE datasheet, it's said that the timebase feature can be used to set the WDGD bit at regular interval...that's strange. So, I will use your method that is more effective. Thanks for your help. Yann [ This message was edited by: Akotronic on 14-04-2005 09:15 ]