Share external bus interfaces

[michaelgaus9]

Posted on November 22, 2005 at 07:14

Share external bus interfaces

[michaelgaus9]

Posted on November 13, 2005 at 07:58

Hello,

I want to share the external bus interfaces of a ST10F269 and a ST10F276 via the HLDEN-functionality. The pins are connected as follows: ST10F269 <=> ST10F276 D0..D15 <=> D0..D15 A0..A19 <=> A0..A19 /RD <=> /RD /WRL <=> /WRL /WRH <=> /WRH ALE <=> ALE /CS0../CS4 <=> /CS0../CS4 /BREQ <=> /HOLD /HLDA <=> /HLDA /HOLD <=> /BREQ The ST10F269 is configured as follows: - master (DP6.7 = 0) - XPERSHARE enabled - XRAM1 (E000-E7FF) enabled - XRAM2 (C000-DFFF) enabled The ST10F276 is configured as follows: - slave (DP6.7 = 1). - XPERSHARE disabled - XRAM1 (E000-E7FF) disabled - XRAM2 (F0000-FFFFF) enabled - BUSCON0: 16-Bit demux Now I want to access the master's XRAM (ST10F269) from the slave (ST10F276), /CS0 should get active for these bus accesses. Sometimes I can read correct data out of the master's XRAM, but sometimes I get wrong read data. Is it necessary to also enable XPERSHARE in the slave? Is it necessary to enable VISIBLE? Are any waitstates needed for the XRAM access? If the slave (XPERSHARE disabled) accesses his own XRAM, is there also a HOLD-Request generated? Thanks, looking

[charles239955_st]

Posted on November 16, 2005 at 05:49

No need to enable XPERSHARE in the slave.

No need for Visible mode. Waitstates not needed, if both ST10 have the same CPU frequency. No Hold request when the slave accesses its own XBus ressources. What do you mean by wrong data read? Some bits are corrupted or whole data is wrong? Is it a data from a different address? Is the data linked to the last data on the Bus?

[michaelgaus9]

Posted on November 16, 2005 at 06:01

>> No Hold request when the slave accesses its own XBus ressources

Are there no bus conflicts in that case when the slave accesses its own XRAM without a hold request? >> What do you mean by wrong data read? Some bits are corrupted or whole data is wrong? Is it a data from a different address? Is the data linked to the last data on the Bus? Sometimes the data read is equal to the value of the startup configuration selected with the pulldowns on Port0. Sometimes whole data is wrong. Data is not linked to the last data on the bus. Does the XRAM use WRL/WRH or WR/BHE? Thanks, looking

[michaelgaus9]

Posted on November 16, 2005 at 14:45

Are there any problems if the pulldowns on Port0 are about 2k2?

I have 4k7 pulldowns on both controllers, so in parallel there is approx. 2k35. Best Regards, looking

[michaelgaus9]

Posted on November 18, 2005 at 09:40

I have a screenshot of a wrong bus access attached.

Signals BREQ, HLDA, HOLD are the signals of the bus slave (ST10F276). Slave wants to access the bus and activates BREQ. Master acknowledges with activating HLDA. After that master seems to set an own bus request by activating HOLD of the slave. But the slave should first complete itw bus access. But why gets BREQ of the slave inactive for a short period (about 20 ns) before the slave bus access is completed? Now there is a bus access conflict between master and slave. Any ideas how to solve the problem? Thanks, looking ________________ Attachments : busarbit.jpg : https://st--c.eu10.content.force.com/sfc/dist/version/download/?oid=00Db0000000YtG6&ids=0680X000006I0N2&d=%2Fa%2F0X0000000bY6%2FMuyQfuzHwxF11m9l0OM1MANHHhJYKX23ulRGEJu6Km0&asPdf=false

[michaelgaus9]

Posted on November 22, 2005 at 07:14

Now I tested the whole thing with two ST10F269 for master and slave and that constellation works without errors.

Are there any known bugs concerning external bus arbitration in the ST10F276 (Step CAA) ? Is there anything different in the initialization between ST10F269 and ST10F276?