Reset function on STR910-EVAL

[yuhleon]

Posted on July 18, 2008 at 09:49

Reset function on STR910-EVAL

[yuhleon]

Posted on May 17, 2011 at 09:41

Hi all ,

I'm using STR910-EVAL board . It has a reset button (PB2). But when I push this button , my program can not restart . My program is FreeRTOS . The datasheet says the Reset has two types : system reset and global reset . The reset button seems the system reset . But system reset cannot restart my program successfully . How can I use global reset and don't need poweroff and poweron my board , just push a reset button ? Thanks.

[najoua]

Posted on May 17, 2011 at 09:41

Hello yuhleon,

Could you please tell me: - What is the operating frequency? - From what bank you are booting? Regards, Najoua.

[yuhleon]

Posted on May 17, 2011 at 09:41

Hi Najoua,

My board frequency is 25000 KHz, and I'm booting from Bank1 . My Bank1 is IAP ( bootloader ) , and Bank0 is my program . Thanks.

[najoua]

Posted on May 17, 2011 at 09:41

Hello yuhleon,

If you are using the IAP driver provided by ST or you are using your own IAP driver in which a software remapping is performed just before jumping to your application in Bank0, so: the behavior you are observing with the hardware reset is normal and considered as a limitation(discovered recently) which will be corrected in the next STR91x IAP release. Please let me clarify: ----- The System Reset (as hardware reset) sets all registers to their reset values EXCEPT the Clock control register (SCU_CLKCNTR), PLL configuration register (SCU_PLLCONF), System status register (SCU_SYSSTATUS) and the FMI Bank address and Bank size registers. Before jumping to the user application, software remapping of Bank0 and Bank1 at 0x00 and 0x80000, respectively, is performed. If a hardware reset is applied, the FMI Bank address and Bank size registers keep the last values corresponding to the software remapping BUT CR register is reset to its default value: 0x8 which means that only Bank0 (mapped at address 0x00) is enabled. Normally, in this case the user application located in Bank0 (address 0x00) should be executed without problems after a hardware reset; but this is not the case. This lets us doubt in the meaning of B0EN and B1EN in CR register: B0EN is Boot bank enable (and not Bank0 enable) and B1EN is non boot bank enable(and not Bank 1 enable). This doubt was confirmed by our Design guys: the meanings of B0EN and B1EN bits are not Bank0 Enable and Bank1 Enable BUT Boot Bank Enable and Non Boot Bank Enable. In this case, using IAP, we will have the following configuration after a hardware reset: - Bank0 mapped at address 0x00 and Bank0 (Non boot bank) is disabled-> application loaded in Bank0 can not start. - Bank1 mapped at address 0x80000 and Bank1 (boot Bank) is enabled-> IAP driver located in Bank1 can not start. A Power On Reset should be applied to reset all FMI registers to their default values in order to be able to boot from Bank1 (A boot from Bank0 is impossible). Note: If the software remapping is omitted from the IAP and simply a jump to the user application at address 0x80000 is performed, the problem with hardware reset doesn't appear. I hope i was clear in my explanation. Best regards, Najoua. [ This message was edited by: Najoua on 12-04-2007 12:48 ] [ This message was edited by: Najoua on 12-04-2007 13:13 ]

[yuhleon]

Posted on May 17, 2011 at 09:41

Thank you Najoua,

I think I understand your explain , if I want to solve this problem , I can : 1. wait ST provide new IAP 2. modify my program and IAP which are not perform remapping I intend the second way to solve the problem . Have you been tried this way successfully ? Regards.

[yuhleon]

Posted on May 17, 2011 at 09:41

Hi all,

I was thinking this problem this few days , and I have some ideas . Because the defferent between System Reset and Global Reset is that there are some registers cannot be reset . The registers are : Clock control register (SCU_CLKCNTR) PLL configuration register (SCU_PLLCONF) System status register (SCU_SYSSTATUS) FMI Bank address and Bank size registers So if I add some code in IAP reset handler that can reset the above registers , it will become the same as global reset . I don't it can work or not .

[najoua]

Posted on May 17, 2011 at 09:41

Hello yuhleon,

Yes, I have tried this way successfully in a case the loaded application in Bank0 doesn't contain interrupts. The situation becomes difficult if the loaded application located at 0x80000 contains interrupts: the interrupt vector must be located at address 0x00. I didn't try this case. Any suggestions are welcome. Regards, Najoua.

[d_steffen]

Posted on May 17, 2011 at 09:41

The simple way is to build a jmp table from the vector table

in flash at adddress 0 to the internal RAM (f.e.) 0x4000000). The bootloader and the application have there own interrupt and exception handlers. The jmp table in RAM is rebuilded if the bootloader or the application starts.

[akaiser9]

Posted on May 17, 2011 at 09:41

As I understand the problem description above, once the IAP places the application bank at address 0 you are lost, because a non-power-up reset disables the flash bank placed there but does not remap the IAP code in the other bank to 0. So there is no longer any code at address 0.

So the only way do deal with this problem is to not remap any flash banks and run the application code at 0x80000+. This is fairly easy as long as the IAP itself does not use any interrupts, aborts or syscalls, because in this case all the vectors except for reset can simply be redirected to 0x80000+. Things get complicated when interrupts are used by IAP. Then a vector table in RAM must be used.