Posted on April 24, 2006 at 12:01Hello!
I have few questions related to peripgeral access times.
I made the simple test (before and after this block IO pin is toggled and this block is excecuted in loop. Known number of commands (messing with registers) where also added to the loop to ease up calculation of cycles. In order to get the number of cycles I added these writes one by one and measured how many cycles where added to the loop):
strh r1,[r12,#0x00]
: +4 cycles
strh r2,[r12,#0x04]
: +4 cycles
strh r1,[r12,#0x08]
: +10 cycles
strh r2,[r12,#0x0C]
: +4 cycles
strh r2,[r12,#0x10]
: +10 cycles
where r12 is pointing to the EIC_ISR (0xFFFFF860). So I noticed that after every second write to the peripheral (which is located on APB), 10 cycles are spent and after every another write access, 4 cycles are spent (MCLK: 48MHz, PCLK1=PCLK2= 24MHz). So it seems to be that APB bridge can accept two sequential write accesses (storing the second one for ''later use''). Correct me, if Im wrong.
The interesting part comes if I insert another command between write accesses where 10 cycles delay is encountered (like assuming there are wait cycles inserted by the APB bridge and trying to excecute some other useful commands instead of another peripheral write), total number of cycles decrease:
strh r1,[r12,#0x00]
: +4 cycles
strh r2,[r12,#0x04]
: +4 cycles
strh r1,[r12,#0x08]
sub r5,r6,#1
: +6 cycles (?)
strh r2,[r12,#0x0C]
: +4 cycles
strh r2,[r12,#0x10]
: +10 cycles
So if another command is excecuted between two writes, wait cycle seems to be shorter? Could anyone please explain this to me as its easier to optimise the code after getting the full understating whats really going on.
I tried to use stm aswell. the result was similar to the prevoious one, except there +4 cycles was replaced by +2, which is understanable as no instruction has to be fetched. It was not possible to add another command between peripheral writes while using stm, naturally.
betst regards,
Madis
