Memory

[shermantec]

Posted on January 08, 2004 at 10:13

Memory

[shermantec]

Posted on May 17, 2011 at 11:57

Hello

With this design I need to use 256Kb External RAM. From what I can see from the data sheet there is only 12 address bits while I need 18 bits. So for the additional 6 I need to use a �banking� switch using the PLD. 1. Is there any other suggestion? 2. The 6 address bits are generated by the PLD from 3 bank select input. So does it occupy 9 chip pins total? 3. If I am using the PLD latch address out function does the ALE latch the address automatically? 4. The data sheet contains a lot of TBD (like current consumption icc-cpu parameter). Is there more update document? Is there any available application notes and samples specific for this device series? Latino

[jdaniel]

Posted on May 17, 2011 at 11:57

Latino,

1. No, there's really no way other than doing some manual switching to select the high-order bits. Even internally, the uPSD only has a 16-bit address bus in conjunction with a page register. 2. The high-order address bytes only need to occupy as many pins as you need. In PSDSoft Express, you can select 6 pins as combinatorial CPLD Outputs. You can then map 4 of these pins to a12, a13, a14, and a15 of the internal bus. Next, you can decide on what page you want this memory to reside and select the appropriate bits from the page register to map to these final two address pins for your application. 3. Yes, the latched address output pins are automatically latched on ALE. Also, although I haven't tried this, I'm pretty sure you can take the afforementioned CPLD output pins and tie their output enable to ALE and achieve a similar effect. 4. I think the TBD in the data sheet for current consumption is because there's a complication formula for it based on how much CPLD logic you're using, whether it's in turbo mode, what your memory access mixture is, etc. Hope some of that helps. Best Regards, pHaze426

[shermantec]

Posted on May 17, 2011 at 11:57

In my design I need to address to an external RAM.

Because the uPSD bus is multiplexed there I need to add a latch for A0-A7. In the attached example I used the CPLD to latch the A0-A7. 1. Is it done automatically (i.e. the CPLD uses the ALE to latch the address)? 2. Where I define that the external bus is 8-bit data bus and not 16 bits? 3. Can you send some info or explain the exact use of cboostX and fsX registers uses? 4. Please check If I assigned A12 to A15 correctly.

[jdaniel]

Posted on May 17, 2011 at 11:57

Latino,

I took a look at your design and there are a few things to note. First, you made a slight mistake in mapping your A0-A7 to port A. You selected the type ''latched address'' from the CPLD INPUT section. You need to go to the box at the bottom of these selections labeled ''OTHER'' and select ''Latched address out.'' Otherwise, the CPLD will take these as an input. And in answer to your question below about ALE, if you change the definition to this type, they WILL be automatically latched on ALE. Also, I noticed you have rs0 and your external RAM chip select mapped to the same memory area, but with only page 0 specified for rs0. This means that when the processor starts up at page 0, it will be accessing the internal RAM and not your external ram until you modify the page register. I'm not sure if this is what you wanted. Also, here are answers to your questions: 2. The external data bus on this chip is always 8-bits since it's an 8-bit architecture. This doesn't need to be defined anywhere. 3. Honestly, the best place to see how these chip select signals are defined is to take a look at AN1560 which describes setting up a project for the DK3200 eval board. 4. It looks like you assigned A12-A15 correctly. One final note is that I didn't see you using any of the page register bits and CPLD outputs to create additional address lines. With a 16-bit address bus, you will only be able to access 64kB of your 256kB external ram. You probably want to define some more pins to let you get at the rest. Best Regards, pHaze426