ISA memory STPC Elite

[mvirique]

Posted on January 05, 2004 at 05:09

ISA memory STPC Elite

[mvirique]

Posted on December 16, 2003 at 12:36

Hello,

I want to use memory on the ISA bus with the STPC Elite. The SDRAM controller on the ISA bus is made with a FPGA. The D0000h-DFFFFh segment is configured with shadow disabled (Shadow Control Register 1 = 00h). This segment doesn't share the flash memory (bit 1 = 0 of Miscellaneous Control Register 1) and ROM Write Protect is enabled (bit 3 = 1). The STPC primary loader allows me to execute an application which writes and reads in the D0000h address. The pattern is AA55h. The problem is that the reads return FFFFh. On the SDRAM bus, I have AA55h. On the ISA bus, SMEMRD# and MEMCS16# are asserted and the value is AA55h. But the STPC returns FFFFh. I tried with an 8 bits tranfer. The reads return FFh. I tried with shadow enabled (thus I work with the SDRAM of the STPC) and the reads return AA55h. Are there other registers to configure? Is there an other problem? Thanks. Cyber

[mvirique]

Posted on January 05, 2004 at 05:09

The problem was about the reset.

The reset was asserted during 60ms. I changed it and now is 300ms (as on the evaluation board). The program works correctly. But in the datasheet (reset sequence), I don't find any information about the minimum time during the reset must be asserted. Which function in the STPC Elite need a signal reset asserted during 300ms? Thanks. Cyber