Posted on January 05, 2004 at 05:09The problem was about the reset. The reset was asserted during 60ms. I changed it and now is 300ms (as on the evaluation board). The program works correctly. But in the datasheet (reset sequence), I don't find any ...
Posted on December 16, 2003 at 12:36Hello, I want to use memory on the ISA bus with the STPC Elite. The SDRAM controller on the ISA bus is made with a FPGA. The D0000h-DFFFFh segment is configured with shadow disabled (Shadow Control Register 1 = 00...
Posted on June 16, 2003 at 06:01Thank you for your explanations. I found some information in the source of linux. But, I haven't yet succeed to load the MBR. I'm probably going to follow your advice. Cyber
