2007-05-07 10:29 AM
2011-05-17 12:41 AM
What's the correct number of wait states for 96MHz? The flash manual is a bit hard to understand - is it 2 wait states above 66MHz and 3 wait states above 75 MHz, or 2 wait states above 75MHz?
Also what's the maximum FMI clock? At 96MHz I was unsuccessful at full FMI clock but successful at half. And if the FMI clock is 48MHz, what is the best setting for waitstates and BUSCFG? 1 wait state and BUSCFG=0 because the FMI clock is now [ This message was edited by: prx on 17-04-2007 20:48 ]2011-05-17 12:41 AM
I tracked it down to a PC-relative load instruction, the first one executed after the clock switch to 96MHz. Stepping though the instructions at full FMI clock fails after this load, succeeds at half FMI clock.
Unsurprisingly, sequential instruction rate is 2 clock cycles per instruction at half FMI clock. So I'm still looking for a sample which runs a full speed. The Hitex demo shipped with the comStick also runs at 96MHz half FMI clock and all other samples I found appear to run at either OSC or 48MHz.2011-05-17 12:41 AM
I don't know if this will help, but I am running with 96MHz, full FMI clock, 3 wait states. I was failing until I changed the code to force the main clock to OSC before changing the PLL config values, then setting the main clock to PLL.
2011-05-17 12:41 AM
@badbarani
It will be very helpfull if you can post a stripped but complete code example. I've never seen code which is running with 96 Mhz FMI clock on the STR91x.2011-05-17 12:41 AM
Was any code ever sent to get FMI running at full clock rate of 96MHz?