Posted on May 17, 2011 at 09:41I don't know if this will help, but I am running with 96MHz, full FMI clock, 3 wait states. I was failing until I changed the code to force the main clock to OSC before changing the PLL config values, then setting the ...

Posted on May 17, 2011 at 09:39Has anyone set up the STR912 for Bulk transfer using the Linked List DMA? I'm hoping to not have to interrupt on every packet to reduce CPU overhead. The LLI seems to work until I reach the short packet at the end of t...