external memory chip

[jones2]

Posted on May 24, 2005 at 12:27

external memory chip

[jones2]

Posted on May 17, 2011 at 12:07

can any one give me any priliminery steps I need to do to connect

more than one uPSD3234a to a shared external RAM.

[jdaniel]

Posted on May 17, 2011 at 12:07

std,

Trying to do this ''on your own'' with a standard RAM chip would be a VERY bad idea indeed. There are devices made just for this purpose, however, called dual-port ram or DPRAM chips. Some popular ones are made by Cypress Semiconductor. Basically, they are RAM chips with a ''left'' and ''right'' address and data bus. They also have built-in arbitration to determine what happens when there are conflicts. For instance, something has to happen when two processors try to write the same location at the exact same time, etc. Take a look at their website and you'll see it's pretty straightforward to implement.

[jones2]

Posted on May 17, 2011 at 12:07

I found the site and chip.

but is there any example of such a driver?

[jdaniel]

Posted on May 17, 2011 at 12:07

std,

There's no simple ''driver'' that's needed for them. Basically, you just have to come up with a set of rules as to how each system's programs can access the shared memory to avoid problems. Some people just use them blindly, but depend on the status outputs to tell them when things go wrong. For instance, here's one idea: Let's say processor A needs to read from the DPRAM, and we don't know if processor B will be writing to it at that time. Let's also assume that we've taken the ''busy'' line of the RAM and run it to an interrupt. I'll have two global flags. One of them called processor_reading_DPRAM and another called read_failed. They'll both be initially false. I'll have the ISR for the interrupt that handles the busy line look like this: if (processor_reading_DPRAM) read_failed = true; Now, in the main code, when I want to read the DPRAM, I'll have: do { read_failed = false; processor_reading_DPRAM = true; memcpy(whatever stuff I need); } while ((read_failed) && (sometimer < sometimeoutvalue)); This will have the program sense if a problem occurred during that read, and just re-do it. You of course need to have some timeout, so the thing doesn't get stuck just because processor B is hogging the memory, and you also need to handle the situation that arises if you timeout. Does that make more sense?

[jones2]

Posted on May 17, 2011 at 12:07

I think dual port RAM support two simultanious read/write access.

I need a RAM that supports more than two, I am thinking somthing like 4 MCU's connected to one RAM.

[jdaniel]

Posted on May 17, 2011 at 12:07

std,

There are ''quadport'' memories, etc. that will allow more accesses to the same bank of storage, but they're not nearly as common as dual-ports. Also, their primary applications seem to fall into networking, so they're usually specialized for those applications. Based on the questions you've asked, I'd suggest abandoning the design that requires 4 MCUs to be connected to one RAM. I think you're going to find it too difficult. What would essentially be required is for you to create your own FPGA or ASIC design to handle all of the ''bus arbitration'' and route the address / data lines after arbitration to a normal RAM. If you have quite alot of money at your disposal, there are probably companies that will sell you an FPGA core that implements the arbitration, but there will probably be royalties / licensing fees etc. that make it prohibitive unless you're going to be selling a huge volume of this product.