Posted on November 02, 2005 at 18:08I am looking at the same question.
In my case the Texas codec TLV320AIC20K or 24K.
ST
must specify the STR7 BSPI behaviour and timing. I think it can be met, but can't be sure what I must do if I don't know what the chip requires. It is impossible to design to an interface that has no spec.
eg, in slave mode:
SCLK high period
SCLK low period
MOSI setup before SCLK
MOSI hold after SCLK
SS setup before SCLK
SS hold after SCLK
MISO delay after SCLK
MISO 3-state delays
Which clock edge is SS sampled on (depends on CPOL & CPHA?)
We assume activity on SCLK and MOSI is ignored if SS is not asserted; and that each new assertion of SS resets the shift register to start a new word.
We know that FCLK>8*SCLK but that's all. Pretty harsh as the last codec I used ran SCLK=5MHz.
The diagrams in the reference manual are wildly inacurate as in some of them a slave brings MISO out of tristate before SS is asserted! I believe it does show Rx data sampled and Tx data changing on opposite clock edges. But the statement that ''SS must be pulled low after the clock is stable'' needs consideration as codecs drive frame syncs on a clock edge.
I have used various codecs before and understand the serial communications. But I have no experience of SPI. I cannot find a published specification for SPI - the term ''SPI'' itself has no definition. It seems that each manufacturer specifies their own style of SPI - I may have used it under another guise like ''microwire''.
If the worst happens I can bit-bash the codec,
if the codec will be a slave and will accept high but intermittent SCLK. One interrupt per sample of 100 instructions won't kill me it's about 3% of the CPU. Two channels is 6% - that's starting to look bad :(
The STR711 han't got many timers to burn for a sample interrupt.
Those Si3000 devices look a lot easier than the TI codecs - in fact mode 0 looks directly compatible. And 3.3V supply only. But I've never heard of the company before.
Anthony
