ADC and power saving

[shinnlin]

Posted on October 22, 2004 at 08:57

ADC and power saving

[shinnlin]

Posted on October 20, 2004 at 16:18

What I want is getting ADC value periodically and having the higher computing power(high MCLK), then entering power saving mode during the rest period.

Is it possible to do this ? Since ADC clock is tied together with MCLK, running from RCLK, I can't keep ADC awake and ask Core to enter WFI, right ? Thus, the best way we think of to do is keeping RCLK fixed, always turn on ADC and switching the MCLK by MCLK divider. Other method to achieve this ? Hope we can have different path, such as RCLK1, RCLK2, to connect CK_AF, CLK3, MCLK, PCLK1 and PCLK2......

[shinnlin]

Posted on October 20, 2004 at 16:30[ This message was edited by: Shinn on 21-10-2004 04:10 ]

[shinnlin]

Posted on October 22, 2004 at 05:04

Thanks, RISC !!

I still have questions : 1. Changing the PCLK2 clock affects the ADC sampling rate. This means that we can't get continuous samples periodically. ( Our sample rate is 500Hz. ) The ''periodical'' means that sample_1 sample_2 sample_3 sample_4 sample_5 |__________|__________|__________|__________| after each sample we wanna do some calculations then enter power saving mode. According to your example, how can we guarantee each sample is periodical since we reset the clock every time. 2. If changing RCLK is allowed, why don't we select CK_AF for low power mode clock ? Regards. [ This message was edited by: Shinn on 22-10-2004 08:42 ]