Posted on July 17, 2007 at 07:31Hello,
I tested the external clock mode of STR755FR0 with following conditions :
// config P1.03 for SCLK input
GPIO_Config(GPIO1, GPIO_Pin_3,GPIO_Mode_IN_FLOATING);
TIM2->CR = 0; // Stop timer, reset mode,
TIM2->CR &= TIM_COUNTER_STOP; // disable timer
TIM2->ARR = 14; // set to count 16 SCLKs
TIM2->CR |= (TIM_COUNTER_MODE_DOWN | TIM_FLAG_UPDATE); // UFS=1, down counter
TIM2->CR |= TIM_COUNTER_RESET; // reset counter
TIM2->SCR = 0x020C; // TS=10, SMS=01, SME=1
TIM2->IMCR |= (1 << 0); // IC1S, IC1 is connected to TI2
TIM2->ISR = 0; // clear pending interrupt flags
TIM2->RSR |= 1; // set update envet
TIM2->RER |= 1; // set update interrupt
The Update Interrupt occured on the 16th rising edge of the clock input.
But from the second interrupt, the update occurred on the 15th rising edge of clock.
I guess the timer counter is initialized to 0xFFFF (but the datasheet says it is zero for reset).
Does somebody know how can I get the update interrupt on every 16th clock from the beginning?
When I set the ARR to 15, the 1st update interrupt occurred on 17th clock, and from the 2nd update,it occurred on 16th clock.
The external clock input is 500kHz.
Best Wishes,
Byung-Tae Jung
