Good day Folks,
I am hoping you are able to shed some light on this odd XSPI clock behaviour. I have connected XSPI2 to a W25Q64 Flash in QSPI mode.
There are 'preamble' clocks present prior to the NCS being asserted. I've noticed that the number of preamble clocks depends on the frequency of the bus. The least I have seen is 150 clocks. As you can see below it's 641 clocks, prior to the NCS falling.
I am guessing the clock is used internal by the XSPI peripheral, however the 'noise' on the bus certainly is undesirable.
This prevents me from using a NCS other than the dedicated NCS pin. Other than that it looks like it creates additional delays in the XSPI transaction, with the reads maxing out about every 30us.
This is with a XSPI read being done in a while(1) loop.
The data is being correctly read when the NCS is low, expected Byte of 0x16:
When the SCK preamble clocks are present I can see the data lines (e.g. IO0 below) go high impedance and rise to the external pullup, until the NCS is asserted.
If you are able to advise on a solution to hide these preamble clocks, it would be great!
I'm assuming that they are also contributing to additional Delays in the successive XSPI reads.
I've attached a super simple project with a XSPI Read in the while(1).
Kindest regards
