2020-03-27 12:53 PM
There does not seem to be anything in the datasheet about set tolerance, or drift over temperature.
https://www.st.com/resource/en/datasheet/lsm6dso.pdf
Assume the INTERNAL_FREQ_FINE is unchanged. It has a step size of .15%, so one would presume the best you can do is around that if it is calibrated.
I am more concerned with the un-calibrated difference, and how that might change over temp.
Thanks.
Solved! Go to Solution.
2020-03-30 05:15 AM
Hi @Panometric , the 40kHz frequency is directly related to the max ODR 6.66kHz: a single data set is composed of 6 data (3 axis accelerometer + 3 axis gyro), so ODR_max x 6 = 40kHz. The INTERNAL_FREQ_FINE is a read-only register and is related to the factory calibration: it's value (step size 0.15%) is related to the jitter ("accuracy"), and has to be related to the ODR currently used. The ODR vs temperature change, from characterization data, is about the same order of magnitude. Regards
2020-03-30 05:15 AM
Hi @Panometric , the 40kHz frequency is directly related to the max ODR 6.66kHz: a single data set is composed of 6 data (3 axis accelerometer + 3 axis gyro), so ODR_max x 6 = 40kHz. The INTERNAL_FREQ_FINE is a read-only register and is related to the factory calibration: it's value (step size 0.15%) is related to the jitter ("accuracy"), and has to be related to the ODR currently used. The ODR vs temperature change, from characterization data, is about the same order of magnitude. Regards
2022-11-22 06:54 AM
Eleon, I think you're missing the point. The question is about accuracy and stability.The device's internal clock frequency equation should include spec on toleranced and temerature drift etc which is totally missing in the datasheet. It's as if the document was written by the software guys. Has ST acually characterised the clock performance?