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Spurious INT2 on LSM6DSMTR

Jason Hendrix
Associate II
Posted on January 17, 2018 at 02:13

I believe I've configured my system (LSM6DSMTR connected to Nordic nRF52382 via I2C) to interrupt on INT2 when the FIFO threshold is reached.  What is happening, is that I get an interrupt when data first appears in the FIFO (status shows 3 samples), then after a while, I get the FTH interrupt with the status showing the FTH number of samples.  I suspect that the first interrupt is the wakeup interrupt I've configured in the MD2 register.  I've configured that so that the FIFO will transition to bypass-to-FIFO  Any suggestions how to eliminate that first interrupt at the processor? 

By the way, I do want INT1 to assert on wakeup.  Not INT2.  

Here's a readback of my registers:

0x1: 0x0

0x2: 0x0

0x3: 0x0

0x4: 0x0

0x5: 0x0

0x6: 0x4E

0x7: 0x0

0x8: 0x1

0x9: 0x80

0xA: 0x24

0xB: 0x0

0xC: 0x0

0xD: 0x0

0xE: 0x8

0xF: 0x6A

0x10: 0x20

0x11: 0x0

0x12: 0x64

0x13: 0x0

0x14: 0x0

0x15: 0x0

0x16: 0x0

0x17: 0x0

0x18: 0xE0

0x19: 0x0

0x1A: 0x0

0x1B: 0x0

0x1C: 0x0

0x1D: 0x20

0x1E: 0x5

0x1F: 0xC2

0x20: 0xED

0x21: 0x3

0x22: 0x0

0x23: 0x0

0x24: 0x0

0x25: 0x0

0x26: 0x0

0x27: 0x0

0x28: 0x43

0x29: 0xFD

0x2A: 0xF8

0x2B: 0xFE

0x2C: 0x58

0x2D: 0x41

0x2E: 0x0

0x2F: 0x0

0x30: 0x0

0x31: 0x0

0x32: 0x0

0x33: 0x0

0x34: 0x0

0x35: 0x0

0x36: 0x0

0x37: 0x0

0x38: 0x0

0x39: 0x0

0x3A: 0x0

0x3B: 0x10

0x3C: 0x2

0x3D: 0x0

0x3E: 0x41

0x3F: 0x41

0x40: 0x41

0x41: 0x0

0x42: 0x0

0x43: 0x0

0x44: 0x0

0x45: 0x0

0x46: 0x0

0x47: 0x0

0x48: 0x0

0x49: 0x0

0x4A: 0x0

0x4B: 0x0

0x4C: 0x0

0x4D: 0x0

0x4E: 0x0

0x4F: 0x0

0x50: 0x0

0x51: 0x0

0x52: 0x0

0x53: 0x0

0x54: 0x84

0x55: 0x0

0x56: 0x0

0x57: 0x0

0x58: 0x90

0x59: 0x0

0x5A: 0x0

0x5B: 0x1

0x5C: 0x2

0x5D: 0x0

0x5E: 0x20

0x5F: 0x20

0x60: 0x0

0x61: 0x0

0x62: 0x0

0x63: 0x0

0x64: 0x0

0x65: 0x47

0x66: 0x0

0x67: 0x0

0x68: 0x0

0x69: 0x0

0x6A: 0x0

0x6B: 0x0

0x6C: 0x0

0x6D: 0x0

0x6E: 0x0

0x6F: 0x0

0x70: 0x0

0x71: 0x0

0x72: 0x0

0x73: 0x0

0x74: 0x0

0x75: 0x0

#lsm6dsm #wakeup #int2 #fifo
Jason Hendrix
Associate II
Posted on January 17, 2018 at 20:06

To put it another way - Can I configure the LSM6DSMTR to trigger the FIFO (in bypass-to-FIFO) on Wakeup and get ONLY the FTH interrupt on INT2?

Posted on January 18, 2018 at 14:35

It seems to me that it is not possible, but I will double check with my colleagues.

Btw. you are using Continous-to-FIFO mode, not Bypass-to FIFO (it is not available).

Posted on January 18, 2018 at 17:40

Thanks.  Please confirm after checking with your colleagues.  You're right that there is no Bypass-to-FIFO mode.  However, I think I'm in Bypass-to-Continuous - register 0xA = 0x24.  Not in Continuous-to-FIFO.

Jason Hendrix
Associate II
Posted on January 19, 2018 at 02:54

I was able to make it work for me by sending the FTH interrupt to INT1 instead of INT2.  In this way I get separate interrupts for Wakeup and for FIFO threshold.

Posted on January 21, 2018 at 14:30

You are right, 0x0A = 0x24 means Bypass-to-Continuous mode.

The wake-up event detection has to be configured using INT2_WU bit of the MD2_CFG, so the wake-up signal will be always present on the INT2 pin.