[Solved] LIS2DH12 Watermark and Overflow Interrupts at the same time (Not possible)

[JSant]

I'm working on a project that uses the LIS2DH12 accelerometer by ST. I have a couple of questions about it, and as it is quite a common part, I wonder if anyone here knows the answers:

I would like to know if it's possible to activate two interrupts, watermark and overflow, in the same pin. I tried to set them up, enabling latching interrupts in INT1 in CTRL_REG5 and setting both watermark and overflow in CTRL_REG3. When I get a watermark register, I read INT1_SRC, but that returns 0 (I would expect it to return 0x80, interrupt active) and it doesn't clear the interrupts. I don't know if the overflow interrupt ever kicks in, as I can't clear the watermark without reading the FIFO (I would expect that by enabling latching interrupts, I could clear the interrupt by reading INT1_SRC, and then leave the samples unread to trigger the overflow interrupt).

In case somebody is asking why would I do this, I'm a bit paranoid, and don't want to miss an interrupt and end up losing data. Also, I know that I have a second INT pin, but I can't use it at the moment.

//Setup code
 
// set increment bit so we can write to multiple registers with one SPI command
accel_transfer_buf[0] = LIS2DH12_REG_CTRL_REG0 | LIS2DH12_MULTI_BYTE_RW;  //The register address will increment on every write
// CTRL_CFG_REG0
accel_transfer_buf[1] = 0x10; //Magic word of the CTRL_REG0, it needs to be that.
// TEMP_CFG_REG
accel_transfer_buf[2] = LIS2DH_settings.tempEnabled;
// CTRL_CFG_REG1
accel_transfer_buf[3] = 0; //Don't write to ctrl1 yet, as that will turn the accelerometer on, do it as the last step in the config
// CTRL_CFG_REG2
accel_transfer_buf[4] = 0; //Disable High pass filters, see AN5005
// CTRL_CFG_REG3
accel_transfer_buf[5] = LIS2DH12_BITS_I1_WTM | LIS2DH12_BITS_I1_OVERRUN; //Interrupts enabled in INT1 pin: watermark and overrun
// CTRL_CFG_REG4
//Block data update enabled(AN5005), big endian, accelerometer range, normal mode 10bit, 4 wire SPI
accel_transfer_buf[6] = LIS2DH12_BITS_BDU | LIS2DH_settings.accelRange | LIS2DH_settings.HiResMode;
// CTRL_CFG_REG5
accel_transfer_buf[7] = LIS2DH_settings.fifoEnabled | LIS2DH12_BITS_LIR1; //enable fifo, interrupts latched
// CTRL_CFG_REG6
accel_transfer_buf[8] = 0; //No int on INT2 pin (it's disconnected anyway). Interrupt polarity set to active High
// REFERENCE
accel_transfer_buf[9] = 0; //Reference for interrupts
 
[...]
 
//Later on...
accel_transfer_buf[10] = LIS2DH12_REG_FIFO_CTRL_REG;
accel_transfer_buf[1] = LIS2DH_settings.fifoMode | ((FIFO_THRESHOLD - 1) & 0x1F);
 
[...]
 
//and finally
accel_transfer_buf[0] = LIS2DH12_REG_CTRL_REG1;
accel_transfer_buf[1] = LIS2DH_settings.accelSampleRate | LIS2DH_settings.HPLPmode | LIS2DH_settings.zAccelEnabled | LIS2DH_settings.yAccelEnabled | LIS2DH_settings.xAccelEnabled;

When I get an interrupt, I do

accel_transfer_buf[0] = LIS2DH12_REG_INT1_SRC | LIS2DH12_READ_REGISTER;
uint32_t errorCode = SPIDRV_MTransferB(spi_handle0, accel_transfer_buf, accel_transfer_buf, 2);
checkErrorCode(errorCode, "DEBUG");
debug_logln(VERBOSE, "Accel Int: 0x%02X", accel_transfer_buf[1]);

And I would expect to get 0x80, but I get 0x00 (and there are no errors in the transfer).

1) Do you know if what I'm doing with the latched interrupts is correct?

2) Do you know if what I'm trying to achieve with the two ints in the same pin is possible?

Thanks!

[Miroslav BATEK]

The status of FIFO interrupts is in FIFO_SRC_REG (2Fh) not in the INT1_SRC!

[JSant]

Hi Miroslav,

Thanks for your quick reply. Yes, I know, to get the status of the active ints and the number of samples in the FIFO I read FIFO_SRC_REG. That works as expected. I set a watermark level of 25 and when I get an interrupt I get 0x99 (0b10011001, which is watermark bit high and 25 samples in the FIFO).

My question was more oriented to clearing the watermark interrupt flag. I tried activating the latching interrupts, and from the datasheet I understood that reading INT1_SRC would return 0100 0000, that is, only the interrupt active bit, and that reading it would clear it, but first it returns 0x00, and it doesn't clear the interrupt. My idea was to try to get the watermark at 25 samples active in INT1, but also the overrun interrupt in INT1 too. Imagine this case: I get the watermark interrupt, but for whatever reason, I fail to attend it. I would like to get another interrupt when the overrun flag is set. In order to get the second interrupt, the overrun, I would need to clear the watermark interrupt. I can clear the flag in the ISR easily, but I can't process the samples as that takes more time.

Coming back to my issue with reading INT1_SRC not clearing the interrupt and returning 0x00. Is it because it only clears the interrupt IF AND ONLY IF the X/Y/Z Low/High interrupts are set? If that's the case, it seems pretty clear that what I want to achieve is not possible, you can't clear the watermark interrupt without reading samples below the watermark level.

PS: I edited my code as it only showed the watermark interrupt being activated by writting to CTRL_REG_5. Now it shows both WTM and OVRN active, which was what I wanted to achieve.

[Miroslav BATEK · Accepted solution]

Yes, it is not possible to clear the WTM and OVRN interrupt by reading INT1_SRC.