Power up timing LIS2DE12

[JFox.1]

Is there any technical data regarding when the FIFO becomes functional after power up? I have noticed I2C comms and registers can be accessed quite quickly but if the FIFO is initialised too early (e.g. going into FIFO mode), it never starts storing data, despite the relevant configuration registers being perfectly correct. My guess is that it is something to do with the need to come out of bypass mode and if this is done too early after power up, it doesn't work. Have any ST support personnel any details?

[Eleon BORLINI]

Hi @JFox.1​ , please consider that the boot procedure is complete within 5 milliseconds after device power-up, as reported in LIS2DE12 datasheet, p. 31. After how many milliseconds do you enter in FIFO mode, starting filling the FIFO itself? Please note also that a common procedure is to discard the 1st acquired sample after power on, in order to avoid any eventual initial discontinuities in the acquisition. Regards

[JFox.1]

Yes, the 5ms on p.31 is what set me banging my head against a wall for a while.

I issue the following commands after POR using I2C:

1) CTRL_REG1 B'01001111'

2) CTRL_REG5 B'01000000'

3) FIFO_CTRL_REG B'01000000'

Then I wait a bit and repeatedly poll FIFO_SRC_REG.

If instructions 1-3 are started 20ms after POR, the instructions are acknowledged and the registers read back with the correct contents but the FIFO never starts filling and FIFO_SRC_REG stays 0x20.

If exactly the same code is issued 45ms after POR, things work as expected.

Thank you for the tip to read and discard the first value. Upon inspection, the value has always appeared to be valid so far.

[Eleon BORLINI]

Hi @JFox.1​ , may it depend on the ODR you set? I mean, for a valid data (both in continuous mode and in FIFO mode), you should wait a time almost equal to 1/ODR. if ODR = 50Hz, the suggested waiting time is at least 20ms. Are you facing the same issue for high ODR? Regards

[JFox.1]

Thank you. It could be but not in any obvious manner to me. The fifo NEVER starts filling if these instructions are given too early. As I say, I have continually polled for at least 2secs (with ODR=50Hz) and nothing appears in the fifo. Perhaps one must wait 1/ODR before turning on FIFO mode from bypass mode after POR? Perhaps one sample needs to have already been done; I don't know. It would be nice to know because then I can be sure that the time criterion has elapsed before I send the instructions. Time waiting unnecessarily is wasted power so it would be nice to know.

So, possibly something to do with, from the datasheet: 'After the last read it is necessary to transit from Bypass mode in order to reset the FIFO content. After this reset command, it is possible to restart FIFO mode just by selecting the FIFO mode configuration...' Although the FIFO_CTRL_REG is set to Bypass at POR, I wonder if it needs some unknown time delay from POR before the reset mechanism is enabled and an acceptable transit to FIFO mode can be made.

[Eleon BORLINI]

Hi @JFox.1​ ,

2 seconds are too much time, there should be something wrong...

You may try to check this code for the LIS2DS12 lis2ds12_multi_read_fifo.c at least to check if your procedure for the FIFO setting is complete (well, it's just a single command...)

  /* Set FIFO watermark to FIFO_WATERMARK */
  lis2ds12_fifo_watermark_set(&dev_ctx, FIFO_WATERMARK);
 
  /* Set FIFO mode to Stream mode (aka Continuous Mode) */
  lis2ds12_fifo_mode_set(&dev_ctx, LIS2DS12_STREAM_MODE);

Do you have the possibility to test a different DUT?

-Eleon

[JFox.1 · Accepted solution]

Thank you, Eleon. Sorry, it looks like this was due to a brief but large spike on the supply, resetting the accelerometer. No problem with the accelerometer at all. Thank you for your help.

[Eleon BORLINI]

Thank you @JFox.1​ for the follow up and the confirmation!

-Eleon