ODR vs Interruption signal IIS3DWBTR

[MSierraA]

Hi Community,

We have the IIS3DWBTR, we made a configuration like the following:

spi_buffer[1] = 0x06;               //power down mode + LPF2 Enable +- 16g
spi_write(CTRL1_XL, 1);
spi_buffer[1] = 0x44;               // bdu: 1, if_inc: 1
spi_write(CTRL3_C, 1);
spi_buffer[1] = 0x2C;               // (int 1 or int 2)--> int1: enable, i2c: disabled
spi_write(CTRL4_C, 1);
spi_buffer[1] = 0x00;               // Disable self-test, no rounding
spi_write(CTRL5_C, 1);
spi_buffer[1] = 0x00;               // offset 2^-10 g/LSB, 3 axis mode --> 0x08 offset 2^-6 g/LSB, 3 axis mode
spi_write(CTRL6_C, 1);
spi_buffer[1] = 0x02;
spi_write(CTRL7_C, 1);
spi_buffer[1] = (CTRL8_ODR_4 | CTRL8_LPF2_HPF_EN);
spi_write(CTRL8_XL, 1);   // Acel bandwidth and low/high pass
spi_buffer[1] = 0x00;               // Timestamp disabled
spi_write(CTRL10_C, 1);
spi_buffer[1] = 0x01;               // int1 DRDY enable
spi_write(INT1_CTRL, 1);
spi_buffer[1] = 0x01;               // int2 DRDY enable
spi_write(INT2_CTRL, 1);
spi_buffer[1] = 0xA6;               // LPF2 Enable +- 16g
spi_write(CTRL1_XL, 1);
delay_ms(100);

then we use the interrupt of the int1 pin to perform measurements, we discard samples according to the descriptions of odr/4, odr/10, etc. but when we perform the FFT of the signal obtained, we realized that for a 2kHz signal the sensor means 1984Hz which made us think that the sensor means a higher frequency than indicated in the datasheet

That is why we carried out an oscilloscope measurement on the interrupt pin and it showed us that the frequency of said pin was 26710 Hz, the datasheet indicates 26667 Hz, is this frequency correct?

@Eleon BORLINI​ can you help us with this?

[Eleon BORLINI · Accepted solution]

Hi @MSierraA​ ,

sorry for the delay in my answer, but yes, you are right: the output ODR can vary from the nominal value of 26.667kHz. And the correct way to detect its actual value is to measure the frequency of the DataReady interrupt.

I can share you some more details to justify this. The internal 5MHz clock have a non zero variability, that reflects on the ODR variation with respect to the nominal value, according the the below histogram:

 

If my reply answered your question, please click on Select as Best at the bottom of this post. This will help other users with the same issue to find the answer faster. 

-Eleon