LIS3DH: How to get FIFO watermark event signalled on INT1

MVale.2 · ‎2021-02-17

I am struggeling to make the INT1 to activate due to a FIFO watermark event.

I have a simple driver so far to ease the design verification testing of our card, and I am just trying to make sure that the INT1 line can be driven active by the LIS3DH.

To do so, I just enable the FIFO in regular FIFO mode and enable the I1_WTM in the CTRL_REG3.

I expect that the INT1 will activate (high or low depending on the INT_POLARITY in CTRL_REG6) when the FIFO fills up to the watermark.

I can see that the WTM in the FIFO_SRC_REG goes 1, but the INT1 line is not driven active.

Is there any order of operations, or anything I am missing? The initialization procedure is like this:

spi_write X, Y, Z, no LP, 1Hz enable: 0x17 to CTRL_REG_1 0x20

spi_write HR enable, FS 16g: 0x38 to CTRL_REG_4 0x23

spi_write BYPASS mode: 0x0 to FIFO_CTRL_REG 0x2e

spi_write FIFO mode and watermark 24: 0x58 to FIFO_CTRL_REG 0x2e

spi_write FIFO enable and LIR INT1: 0x48 to CTRL_REG_5 0x24

spi_write FIFO watermark on INT1: 0x4 to CTRL_REG_3 0x22

Thanks in advance for you attention.

Regards

Miguel Valero

Embedded SW developer in Aker Solutions AS, www.akersolutions.com

MVale.2 · ‎2021-02-18

I forgot to mention that it is not only that the INT1 line does not go active. The IA bit in the INT1_SRC is not set either.

I have also tried enabling both the I1_WTM and the I_OVERRUN in the CTRL_REG3, but still no IA bit in INT1_SRC either on watermark or on overrun (while the FIFO_SRC_REG signals them).

Another thing I wonder is that the INT1 line does not go high when inactive if I change the INT_POLARITY in CTRL_REG6.

I would expect that when setting INT_POLARITY to 1 (i.e. high, so active low) the INT1 line would go high when no interrupt is active. However, that does not happen.

I really wonder what I am doing wrong.

Any experience with this out there?

Thanks.

CCard.5 · ‎2022-01-25

Hi,

Have you solved that issue? I find myself in the same situation, what I do is read in a while loop whenever there is data in the fifo and see over the scope if the int1 signal is working....but it never goes low, only stays high.