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LIS3MDLTR Data Ready (DRDY) on INT pin

Associate II

Hi! I've got a product that we've just made a load of and while building out the firmware I realised that the INT pin on the LIS3MDLTR doesn't (at least according to the datasheet) appear to be able to be configured to show when new data is ready. The DRDY pin seems to be required for that, and it hasn't been connected in our design.

Is there any magic way of using INT as a DRDY pin, like a hidden register value that could be changed?

Failing that, are INT/DRDY open drain outputs? We have very limited IO on our MCU, but could we short them together in a revised design?


  • Gordon

ST Employee

Hi @gw​ , on LIS3MDL (differently than on other products), you cannot route the DRDY signal on the INT pad, but you can check the DRDY status for all the three axis polling the STATUS_REG (27h) with your SPI/I2C master (p.28 of the datasheet:(

  • ZYXDA bit raise to logic '1' when X-, Y- and Z-axis new data available;
  • ZDA bit raise to logic '1' when Z-axis new data available;
  • YDA bit raise to logic '1' when Y-axis new data available;
  • XDA bit raise to logic '1' when X-axis new data available.

Btw, INT/DRDY are open drain, so they can be left floating. On the other hand, pins like PIN2 and PIN12 (reserved pins) must be connected to GND.


Associate II

Hi Eleon,

Thanks for the answer. This is for a low power device so I'd like to avoid polling if at all possible.

Looks like I'm out of luck then. If I were to connect DRDY/INT in a board respin, is it possible to disable DRDY in software?

:( you can try to minimize the current consumption acting on the ODR and workign in Idle mode (MD1 of CTRL_REG3 equal to 1). You can check also the AN4602 if it can be of your help... Regards

Hi Eleon,

Knowing that INT/DRDY are open drain is very helpful, where on this datasheet does it say this?