IIS2DH: Is it possible to use INT2 pin for FIFO OVERRUN (stream mode)?

[RPool.1]

I am trying to use INT2 pin for FIFO overrun in stream mode because I am dumb and have ONLY connected INT2 to my MCU. INT1 is NC. Trying to avoid a new board.

The datasheet seems to contradict itself but I expect I am missing something. I have tried all combinations of these three register bits:

• CTRL_REG3[I1_OVERRUN] enables FIFO overrun on INT1
• CTRL_REG6[I2_INT1] states "Interrupt 1 function enable on INT2 pin."
• FIFO_CTRL_REG[TR] "1: trigger event allows triggering signal on INT2"

I would have thought setting these bits would achieve my goal but it doesn't seem to. Is this component able to trigger FIFO overrun interrupt on pin INT2?

Many thanks.

[Eleon BORLINI · Accepted solution]

Hi @RPool.1​ ,

I'm afraid that, for certain interrupts such as the I1_OVERRUN one, they are directly tied to the INTx pin when they are enabled, and that the "Interrupt 1 function enable on INT2 pin" possibility is valid only for a specific class of interrupts, specifically the INT1_SRC (31h) and the INT2_SRC (35h) flags.

This because the CTRL_REG3 (22h) interrupts are already sent to the physical INT1 pin, and are not mapped in an equivalent register with their proper flag.

But I would be happy if you would have found an alternative solution in these days.

If my reply answered your question, please click on Select as Best at the bottom of this post. This will help other users with the same issue to find the answer faster.

-Eleon

[RPool.1]

Thank you. You have saved me a lot of time.