2018-02-09 07:32 AM
Hi,
I am working with H3LIS331DL sensor . my configuration is as follows
This scenario is working fine. we are sampling after getting the data ready interrupt.
I have some special cases where i am facing some issues.
if there is some delay in step 2 and step 3 due to some other register configuration example configuring thecontrol register 4 then (in between step 2 and 3)i am not getting the data ready interrupt. This is one issue.
Next one is after step 4 if get data ready interrupt in case if i delayed to clear the data ready interrupt by reading the data for more than 3 msec then next data ready interrupt is not triggering.
could you help me is there is sequence needs to be followed?
or what could be the reason for the above 2 issues.
thanks in advance.
with Regards,
Thangaraj.P
Note: this post was migrated and contained many threaded conversations, some content may be missing.2018-02-14 06:29 AM
Only setting of two registers is needed to make this functional.
CTRL_REG1 = 0x3F
CTRL_REG3 = 0x02
The communication should look like this:
I suppose you are reading the data too slowly, so new data are available earlier than you read all registers or you are not reading all output registers so the DRDY is not cleared. Please check you communication with scope or logic analyzer and eventually share it with me.
You can also try to reduce the the ODR.
2018-02-14 07:13 AM
Hi,
As i already mentioned this is working fine.But the below configuration in the below sequence is the issue what i am explained above
CTRL_REG1 = 0x3F
CTRL_REG1 = 0x80
CTRL_REG3 = 0x02