2016-11-29 02:46 PM
Hi support,
We wonder if there is any register configuration that allow us to route the motion detection to the INT1 pin and the free-fall detection to the INT2 pin and both working at the same time? Both pins are routed/connected to our uP and we need to have these two features enabled and working at the same time.Thanks in advance2016-12-06 02:48 AM
Yes, this configuration is possible.
You should enable interrupt generator (AOI1) on interrupt pin INT1 (CTRL_REG3 0x22h) and interrupt generator (AOI2) on interrupt pit INT2 (CTRL_REG6 0x25h).
Then configure interrupt generator according to you needs. Configuration of INT1 is described in the datasheet, check registers INT1_CFG, INT1_SRC, INT1_THS, INT1_DURATION. Below is the list of registers for INT2 which are not in the current version of the datasheet but will be published soon.
Please also check application note
http://www.st.com/resource/en/application_note/cd00290365.pdf
for details about free fall and wake-up interrupt configuration.INT2_CFG (34h)
AOI -> AND/OR combination of interrupt events. Default value: 0
6D -> 6-direction detection function enabled. Default value: 0.
ZHIE ->Enable interrupt generation on Z high event. Default value: 0
ZLIE ->Enable interrupt generation on Z low event. Default value: 0
YHIE ->Enable interrupt generation on Y high event. Default value: 0
YLIE ->Enable interrupt generation on Y low event. Default value: 0
XHIE ->Enable interrupt generation on X high event. Default value: 0
XLIE ->Enable interrupt generation on X low event. Default value: 0
INT2_SRC (35h)
0-> do not change
IA->Interrupt active.
ZH->Z high. Default value: 0
ZL->Z low. Default value: 0
YH->Y high. Default value: 0
YL->Y low. Default value: 0
XH->X high. Default value: 0
XL->X low. Default value: 0
INT2_THS (36h)
THS[6:0] ->
1 LSb = 16 mg @ FS = 2 g
1 LSb = 32 mg @ FS = 4 g
1 LSb = 62 mg @ FS = 8 g
1 LSb = 186 mg @ FS = 16 g
INT2_DURATION (37h)
D[6:0] 1 LSb = 1/ODR (Duration time is measured in N/ODR, where N is the content of the duration register.)