Accelerometers in time-interleaving mode: problems and solutions

[Dfsd .1]

Hello!

I have multiple LIS2DS12 accelerometers; according datasheet, it is possible to get data rate high as 3200 and even 6400 Hz. In both cases there are built-in filter with 1420 or 2840 Hz cutt-off frequency. As this accelerometer have internal multiplexer, I can expect a sampling frequency ODR*3 for each channel (X,Y,Z). In all cases build-in filter reject all signal components in range higher then F(sampling)/2.

But, it is way to increase accelerometer bandwidth by using, for example, more then one. In this case they should start with delay. It is look like easy to implement using timer of MCU, especially when accelerometer work in FIFO mode. The frequencies seems to be is not so high to worry about jitters, delays and other stuff. The expected bandwidth should be near ODR*N (N - number of used devices) but LPF of each accelerometers should place constrains on bandwidth too.

But:

1) in my board accelerometers placed rather compact but not in same point. What can I do to solve it?

2) I have a "blind" point at frequency near ODR. For example, if final F(s) should be 12800 Hz for 4 accelerometer, the signal of frequency near 3000...3400 Hz is rejected. It is possible to recover it?

3) Output signal seems to be so noisy, but this may be a consequence of point 1 (placing of accelerometers) which leads to variety of gain.

4) FFT of measured signal seems to have parasitic bins in zone between 3200 to 6400 Hz for F(sampling)=12800 Hz.

What further steps should I do? The goal to archive possibility of analyze spectrum of signal at band above 5kHz.

[Eleon BORLINI]

Hi @Dfsd .1​ ,

let me first check if I well understood your point. You would like to overcome the limitation of bandwidth for the LIS2DS12 (limited both by ODR/2 and by the LP filter cut-off frequency). and, to achieve this, you would like to use multiple devices and synchronize them with a predefined small delay < 1/(ODR/2). Honestly, I don't know if it actually can work, but it looks a clever solution.

To improve your application form an "hardware" point of view, you could think to solder -for example- two accelerometers one on the top layer and one on the bottom layer of your board, exactly under the first accelerometer, and use a thin pcb to minimize the inter-device distance. Don't know however if the constrains of your application can allow this kind of solution.

I agree with you that the jitter is at least one order of magnitude less than the acquisition mismatch. But you have to check whether the actual ODR of your LIS2DS12 is close to the nominal one, for example 3400kHz. It could differ from the typical also of 5%: a way to verify it is to enable the DRDY interrupt and count it.

I'm wondering also if summing two waves at the same frequency might end in some blind zones... you might think to use two (very) different ODRs and check if you get again blind zones, or this effect is more spread out inside the bandwidth...

Let me know if you can do some progresses.

-Eleon