Inquiry Regarding Teseo-LIV3 Ant-off Signal Behavior

[Kento]

I have a question regarding the Teseo-LIV3.

My understanding is that when power is supplied to the IC,

the Ant-off signal should go high (H) after a certain period.

However, in my case, the Ant-off signal remains low (L) even after powering the IC.

Aside from a possible antenna short circuit, what other factors could cause this behavior?

[GalaxyQuest]

Hi,

Maybe the first thing to check is to see if the module is running.

Are you getting PPS output?

Have you checked if you are getting any UART/I2C data even thought it might be blank data for satellites?

[Kento]

Hi,

Thank you for your suggestions.

I am not receiving any PPS output.
The UART terminal remains high after powering on (I am not using the I2C terminal).

To provide more context, we are currently facing defects in some of the products that utilize this IC, and we have confirmed that the IC is not functioning correctly. We are in the process of isolating which part of the circuit is causing the issue.

Based on these observations, do you have any further advice?

[GalaxyQuest]

Hi Kento,

Having no PPS output and not seeing any NMEA data is indication that device is not powering up.

Have you checked your power supply ? Is it constant and not a lot of noise on the lines?

Are you applying power to VBAT?

Are you designing with Teseo LIV3F or Teseo LIV3FL?

If you are designing with Teseo LIV3F, refer to this hardware manual below,

https://www.st.com/resource/en/user_manual/um2231-teseoliv3-gnss-module--hardware-manual-stmicroelectronics.pdf

If it is Teseo-LIV3FL, refer to this manual below

https://www.st.com/resource/en/user_manual/um2980-hardware-specifications-for-teseoliv3fl-stmicroelectronics.pdf

You can private message me your schematic.

I notice you are from JPN, have you gotten in touch with local ST sales and marketing to see if it can be addressed from the JPN region itself?

Thank you.

[GalaxyQuest]

Hi Kento,

I wanted to follow-up on troubleshooting the problem you had mentioned.

From your post I understand you might be working on a production design hence the suggestion to reach out JPN ST sales and marketing.

Therefore, could you please let me know if you have made progress on identifying the problem?

[Kento]

Hi,

Sorry for the delayed response. Due to scheduling on my end, I’ll be reaching out to STMicroelectronics Japan on Monday. I’ll also make sure to update this thread with any progress. I appreciate your helpful advice.

To address your previous questions:

Power supply: I’ve checked it thoroughly—there’s no noise, and the voltage is stable.
VBAT: Yes, power is being applied to VBAT.
Model: I’m working with the Teseo LIV3FL.
Unfortunately, I’m unable to share the schematic due to certain constraints, but the board design was based on your Teseo LIV3FL hardware manual.

My assumption is that the IC itself is unlikely to be damaged. If I could understand the operational flow until the PPS signal (or Ant-off pin) becomes active, it may help pinpoint any potential issues in the board’s implementation.

Thank you for your continued support.

[GalaxyQuest]

Hi Kento,

Thank you for letting me know.

Sounds good, by connecting with local ST JPN team, you can share schematics or talk to a FAE. I am based in US.

Meanwhile, if you get time, another thing to check would be RESET line behavior to make sure it is pulled up and NOT toggling. Toggle of RESET line can cause the module to reset or stay in reset.

Have a good weekend.