2022-04-18 02:30 AM
Hello, there may be mistake in ST library. In reference manual registers are like that.In the library SEMA4_RSTGT has two different addresses for read and write but those are in the same address.
With this when I try to reset gate it goes to one of error handlers, if I comment out RSTGT_W I can reset gates without any problem.
Solved! Go to Solution.
2022-04-25 02:11 AM
Hello,
you are right this is an error in definition.
You can use this new definition instead of:
/**************************************************************************/
/* Module: SEMA42 */
/**************************************************************************/
struct SEMA42_tag {
union {
vuint8_t R;
struct {
vuint8_t unused_0:4;
vuint8_t GTFSM:4;
} B;
} GATE[16];
vuint8_t ADR_reserved0[48];
union {
vuint16_t R;
struct {
vuint16_t RSTGDP:8;
vuint16_t RSTGTN:8;
} B;
struct {
vuint16_t unused_0:2;
vuint16_t RSTGSM:2;
vuint16_t RSTGMS:4;
vuint16_t RSTGTN:8;
} B_read;
} RSTGT_W;
#define RSTGT_R RSTGT_W
};
Thank you for this report.
Best regards,
-Olivier
2022-04-25 02:11 AM
Hello,
you are right this is an error in definition.
You can use this new definition instead of:
/**************************************************************************/
/* Module: SEMA42 */
/**************************************************************************/
struct SEMA42_tag {
union {
vuint8_t R;
struct {
vuint8_t unused_0:4;
vuint8_t GTFSM:4;
} B;
} GATE[16];
vuint8_t ADR_reserved0[48];
union {
vuint16_t R;
struct {
vuint16_t RSTGDP:8;
vuint16_t RSTGTN:8;
} B;
struct {
vuint16_t unused_0:2;
vuint16_t RSTGSM:2;
vuint16_t RSTGMS:4;
vuint16_t RSTGTN:8;
} B_read;
} RSTGT_W;
#define RSTGT_R RSTGT_W
};
Thank you for this report.
Best regards,
-Olivier